3.0 Registers
CX28394/28395/28398
3.6 Interrupt Enable Registers
Quad/x16/Octal—T1/E1/J1 Framers
00E—Error Interrupt Enable Register (IER5)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
TSLIP
RSLIP
—
—
CERR
SERR
MERR
FERR
TSLIP
Enable TSLIP Interrupt
Enable RSLIP Interrupt
Enable CERR Interrupt
Enable SERR Interrupt
Enable MERR Interrupt
Enable FERR Interrupt
RSLIP
CERR
SERR
MERR
FERR
00F—Count Overflow Interrupt Enable Register (IER4)
7
6
5
4
3
2
1
0
LOF
COFA
SEF
BERR
FEBE
LCV
CRC
FERR
LOF
Enable LOF Count Overflow Interrupt
Enable COFA Count Overflow Interrupt
Enable SEF Count Overflow Interrupt
Enable BERR Count Overflow Interrupt
Enable FEBE Count Overflow Interrupt
Enable LCV Count Overflow Interrupt
Enable CRC Count Overflow Interrupt
Enable FERR Count Overflow Interrupt
COFA
SEF
BERR
FEBE
LCV
CRC
FERR
Table 3-7. Counter Overflow Behavior
IER4
LATCH_CNT
Addr 046
Count (addr 050–05A)
Latch
MIR*
Active
Addr 00F
Saturate
Clear
0
1
0
1
0
0
1
1
Hold all Ones
Rollover
hi @rd_LSB
hi @rd_LSB
onesec
hi @rd_MSB
hi @rd_MSB
None
None
@rollover
None
Hold all Ones
Rollover
onesec
none
@rollover
3-24
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
