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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Circuit Description  
CX28394/28395/28398  
2.5 Microprocessor Interface  
Quad/x16/OctalT1/E1/J1 Framers  
2.5.4 Device Reset  
The device contains four reset methods:  
1. Internal Power-On Reset (POR),  
2. Hardware Reset which uses the RST* pin,  
3. Global Software Reset which uses the GRESET bit in register FCR [addr  
080], and  
4. Software Reset which uses the RESET bit in register CR0 [addr 001].  
All four methods result in device outputs placed in a high-impedance state and  
configuration registers set to default values as shown in Table 3-4, Address Map.  
In all reset methods, SYSCKI must be present during the reset process for proper  
operation. MCLK (internal or external) performs the actual register initialization.  
Therefore, if the SYNCMD pin is connected high to enable external MCLK, the  
external MCLK must be applied during reset, and if the SYNCMD pin is low  
during reset, the internal clock (33 MHz) is used and external MCLK is not  
required. After hardware reset, software reset, or internal power-on reset, the  
microprocessor must initialize the configuration registers to the desired state.  
An internal POR process is initiated during power-up. When VDD has  
reached approximately 2.0 V, the internal reset process begins and continues for  
100 SYSCKI cycles if SYSCKI is applied. If SYSCKI is not present, the device  
remains in the reset state and does not terminate until detecting 100 SYSCKI  
cycles. GRESET or RESET can be monitored to determine when POR is  
complete. MCLK (internal or external) must be present during the POR  
concurrent with SYSCKI to allow register initialization.  
Hardware reset is initiated by bringing the RST* pin active (low) for a  
minimum of 4 µs. If SYNCMD is high (using external MCLK), external MCLK  
must be present while RST* is low to allow register initialization. After RST* is  
deactivated, the internal reset process continues for 5 µs and register access  
should be avoided. GRESET can be monitored to determine when the reset  
process is complete.  
2-58  
Conexant  
100054E