CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.5 Microprocessor Interface
The IRR bits from each framer are gated with the corresponding enable bit in
the master interrupt enable register [MIE; addr 01E] and are routed to the master
interrupt register [MIR; addr 01D]. MIE provides a convenient location to enable
or disable interrupts for an entire framer. The serial done bit [SER_STAT;
addr 024] is gated with the serial interrupt enable bit [SER_CONFIG; addr 025]
to produce an additional interrupt request. Finally, MIR bits and the LIU serial
interface interrupt request are combined to generate a single interrupt request
signal on the INTR* pin.
Using these registers, the microprocessor can process interrupts as follows:
Interrupt service routine
1. Read MIR and SER_STAT registers to determine which framer or framers
caused the interrupt or whether LIU serial operation occurred.
2. For each interrupting framer, read IRR to determine which ISR contains
the interrupt event or events.
3. Read the ISR and mask the interrupt event bit using the corresponding IER
to determine which event or events caused the interrupt.
4. Enter the appropriate service routine.
Figure 2-28. Interrupt Generation Block Diagram
Framer 8
Framer 7
SER_DONE
SER_IER
Framer 6
Framer 5
Framer 4
Framer 3
Framer 2
Framer 1
INTR*
MIR
Register
Events
ISR
Latches
IRR
Register
IER
Registers
MIE
Register
NOTE(S):
(1)
In CX28395, INTR1* is provided for Framers 1-8, and INTR2* is provided for Framers 9-16.
100054E
Conexant
2-57
CONEXANT [ CONEXANT SYSTEMS, INC ]
