2.0 Circuit Description
CX28394/28395/28398
2.4 Transmitter
Quad/x16/Octal—T1/E1/J1 Framers
2.4.2.6 Programming
the Data Link Controller
The Transmit Data Link Controller can be programmed according to the system
CPU bandwidth. For systems with sufficient CPU bandwidth, the data link status
can be polled, and the 64-byte transmit FIFO buffer can be used as a single-byte
transmit buffer. For systems with limited CPU bandwidth, the data link can be
interrupt-driven, and the entire 64-byte transmit FIFO buffer can be used to store
entire messages. See Figures 2-22 and 2-23 for a high level description of polling
and interrupt-driven Transmit Data Link Controller software.
The device uses a hierarchical interrupt structure, with one top-level interrupt
request register directing software to the lower levels (see Master Interrupt
Request register; addr 081 and Interrupt Request register; addr 003). Of all the
interrupt sources, the two most significant bandwidth requirements are signaling
and data link interrupts. Each data link controller has a top-level interrupt status
register that reports data link operations (see Data Link 1 and 2 Interrupt Status
registers [ISR2; addr 009, and ISR1; 00A]). The processor uses a three-step
interrupt scheme for the data link:
1. Read the Master Interrupt Request register to determine which framer is
interrupted.
2. Read the Interrupt Request register for that framer.
3. Use that register value to read the corresponding Data Link Interrupt
Status register.
Figure 2-22. Polled Transmit Data Link Processing
Message
Block 1
Transmit Message
0x00
0x20
0x40
Write Block/Byte to FIFO
Block 2
Block 3
If
Yes
End of
Message
No
Wait N Milliseconds
Read FIFO Status
Write End of Message Register
Return
If
No
FIFO Empty
or Near
Empty
Yes
2-44
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
