CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.4 Transmitter
2.4.2.3 Time Slot and
Bit Selection
Time slot and bit selection is done through the DL1 Time Slot Enable [DL1_TS;
addr 0A4] and DL1 Bit Enable [DL1_BIT; addr 0A5] registers. DL1_TS selects
which frames and which time slot will be overwritten. The frame select allows
TDL1 to overwrite the time slot in either all frames, odd frames, even frames, or
in a special 2 kbps mode. The time slot word enable is a value between 0 and 31
that selects which time slot will be filled with data from the transmit data link
buffer. DL1_BIT selects which bits will be overwritten in the time slot selected.
Table 2-5 lists commonly used data link settings.
Table 2-5. Commonly Used Data Link Settings
Data Link
Frame
Time Slot
Time Slot Bits
Mode
ESF FDL
T1DM R Bit
SLC-96
Odd
All
0 (F-bits)
Don’t Care
00000010
Don’t Care
11111111
00001000
FCS
FCS
24
Even
All
0 (F-bits)
Pack6
FCS
ISDN LAPD
CEPT Sa4
N
1
Odd
FCS
NOTE(S): N represents any T1/E1 time slot.
2.4.2.4 Transmit Data
Link FIFO Buffer
The Transmit Data Link FIFO #1 [TDL1; addr 0AD] is a versatile, 64-byte buffer
that can be used as a single-byte transmit buffer or for any number of bytes up to
64. As a single-byte FIFO, the Transmit FIFO Empty Status (TMPTY1) in TDL
#1 Status [TDL1_STAT; addr 0AE] and Transmit FIFO Empty Interrupt
(TEMPTY) in Data Link 1 Interrupt Status (ISR2; addr 009] can be used to do
byte-by-byte transmissions.
Using the Transmit Data FIFO, an entire block of data can be transmitted with
very little microprocessor interrupt overhead. Block transfers to the FIFO can be
controlled by the Near Empty Threshold in the FIFO Empty Control register
[TDL1_FEC; addr 0AB]. The Near Empty Threshold is a user-programmable
value between 0 and 64 that represents the minimum number of bytes that can be
left in the transmit FIFO before near empty is declared. Once the threshold is set,
the Near Empty Status (TNEAR1) in TDL #1 Status [TDL1_STAT; addr 0AE]
will be asserted whenever the Near Empty Threshold is reached. An interrupt,
TNEAR in the Data Link 1 Interrupt Status register [ISR2; addr 009], is also
available to mark this event.
2.4.2.5 End of Message
Once an entire message is written to the transmit FIFO or circular buffer, the
processor must indicate the end of message by writing any value to the TDL #1
End Of Message (EOM) Control [TDL1_EOM; addr 0AC]. In FCS mode, the
EOM indicates that the FCS is to be calculated and transmitted following the last
byte in the FIFO. In the circular buffer mode, the EOM indicates the end of the
transmit circular buffer.
100054E
Conexant
2-43
CONEXANT [ CONEXANT SYSTEMS, INC ]
