欢迎访问ic37.com |
会员登录 免费注册
发布采购

CX28333-1X 参数 Datasheet PDF下载

CX28333-1X图片预览
型号: CX28333-1X
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双/三E3 / DS3 / STS - 1线路接口单元 [Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit]
分类和应用: 电信集成电路PC
文件页数/大小: 68 页 / 549 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
 浏览型号CX28333-1X的Datasheet PDF文件第40页浏览型号CX28333-1X的Datasheet PDF文件第41页浏览型号CX28333-1X的Datasheet PDF文件第42页浏览型号CX28333-1X的Datasheet PDF文件第43页浏览型号CX28333-1X的Datasheet PDF文件第45页浏览型号CX28333-1X的Datasheet PDF文件第46页浏览型号CX28333-1X的Datasheet PDF文件第47页浏览型号CX28333-1X的Datasheet PDF文件第48页  
2.0 Functional Description  
CX28331/CX28332/CX28333  
2.3 Receiver  
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit  
When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs  
are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then  
decoded by the Framer or other downstream device. Line code violations are not  
detected in this mode of operation. The decoder is configurable for either:  
E3 mode using HDB3 coding (E3MODE = 1)  
DS3/STS-1 mode using B3ZS coding (E3MODE = 0)  
The receiver digital data outputs are centered on the rising edge of RCLK  
(see Section 2.9).  
2.3.7 Data Squelching  
A counter in the receiver keeps track of the number of consecutive symbol  
periods without a valid data pulse. When 128 or more 0s in a row are counted, the  
receiver assumes that it has lost the signal and resets itself to try and regain the  
signal. While the receiver is reacquiring the signal, the clock recovery block locks  
to the reference clock and the data squelching is achieved by forcing the data bits  
to zero. The data squelching is true in both NRZ and dual rail mode. When the  
input signal has been properly amplified and equalized, the clock recovery PLL  
will then switch to the incoming data.  
2-12  
Conexant  
100985A  
 复制成功!