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CX28333-1X 参数 Datasheet PDF下载

CX28333-1X图片预览
型号: CX28333-1X
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双/三E3 / DS3 / STS - 1线路接口单元 [Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit]
分类和应用: 电信集成电路PC
文件页数/大小: 68 页 / 549 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX28331/CX28332/CX28333  
2.0 Functional Description  
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit  
2.3 Receiver  
2.3.4 The PLL Clock Recovery Circuit  
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced  
data and provides this clock and the retimed data to the decoder (data mode).  
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference  
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to  
lock to the correct data rate (reference mode). During reference mode, the data  
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a  
valid input is detected.  
2.3.5 Loss Of Signal (LOS) Detector  
The Receive Loss Of Signal (RLOS) is a digital function which monitors the  
retimed data from the clock recovery block. The AMI data is checked for a  
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes  
occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count  
is made on every block of 128 AMI symbols. The RLOS signal is deasserted  
when the 1s count within a block of 128 symbols is at least:  
B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)  
HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)  
The RLOS detector will always monitor the cable-side RX inputs. The  
detector is not affected by the state of remote or local looping.  
2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector  
In the CX2833i device, when ENDECDIS = 0 (encoder/decoder enabled), the  
decoder takes the output from the clock recovery circuit and decodes the data  
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then  
sent out of the CX2833i over the RNRZ (RPOS) pin. Any detected Line Code  
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The  
RLCV pin is asserted for one symbol period at the time the violation appears on  
the RX output pin (RNRZ).  
The following shows data sequence criteria for LCV; violations are indicated  
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation  
(non-alternating positive or negative) pulse is indicated by a V.  
Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are  
passed on as 0 data on the RNRZ pin.  
Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V  
(B3ZS and HDB3). These violations are passed on as 1 data on the RNRZ  
pin.  
Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of  
Bs since the last valid 0 substitution V (follows coding rule). These  
violations are passed on as 0 data on the RNRZ pin.  
The even/odd counter (used to count the number of Bs between Vs) will count  
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the  
counter.  
100985A  
Conexant  
2-11  
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