2.0 Functional Description
CX28331/CX28332/CX28333
2.5 Additional CX2833i Functions
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.5 Additional CX2833i Functions
2.5.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for current generation exists, only one band gap voltage can be used. The
band gap from Ch1 has been chosen for this task.
The 12.1 kΩ external resistor from pin RBIAS to ground, is specified to have
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.
NOTE: Capacitance should be kept to a minimum on the RBIAS pin.
2.5.2 Power-On Reset (POR)
A POR function is provided in the CX2833i device to ensure all of the resettable
digital logic and analog control lines are starting from a known state. This circuit
uses a fixed RC timer (~1µs); additionally, 128 clocks from REFCLK are counted
(after the RC timer has timed-out) before reset is deasserted, which begins timing
after a minimum supply voltage is reached (see Table 2-4).
2.5.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CX2833i allow for local loopback
(terminal or framer side), remote loopback (cable side), or both (the AIS signal
follows the same path as the transmit data during loopback). The RLOS signal
monitors the RX cable inputs irrespective of any loopback.
In remote loopback, set by asserting pin RLOOP high, the receive data
(retimed after clock recovery but not decoded) loops back into the pulse shaper in
place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and
RCLK pins.
In local loopback, set by asserting pin LLOOP, the transmit data loops back
immediately from the encoder output to the decoder input in place of the received
data. Additionally, this data is sent out the TLINEP and TLINEM/N pins.
2-16
Conexant
100985A