CX25870/871
Appendix E HDTV Output Mode
Flicker-Free Video Encoder with Ultrascale Technology
E.7 720p Support with Character Clock Based Data Masters
E.7 720p Support with Character Clock Based
Data Masters
Character clock based graphics controllers with 8 pixel clocks per character will
experience difficulty supporting the 720p ATSC resolution. The reason for this is
because the total line length (i.e., Samples per Total Line = S/TL) of 1650 pixels
for 720P is not evenly divisible by 8. Thus, each line is comprised of an amount of
characters that contains a non-zero fraction (206 + ¼ of a character or 206.25
total characters). To get around this shortcoming, the graphics controller must set
its total line length to 1648 (HTOTAL) pixels and change the pixel clock
frequency to 74.1600 MHz. instead of the values of 1650 pixels and 74.2500
MHz. respectively as specified in the SMPTE-296M standard that governs the
720p resolution.
All of the analog timing will then fall within the guidelines listed in the
SMPTE-296M specification and the CX25870 will generate the desired analog
representation of the 720p ATSC resolution.
Internal analysis of different portions of the 720p R/G/B and Y/PB/PR
waveforms has revealed that this approach is valid. All of the analog timing falls
within the tolerances of the SMPTE-296M standard including the length of the
broad pulse. In terms of clock periods, using the 74.1600 MHz. clock yields a
broad pulse length in time of 20.766 µs in duration. Using a 74.2500 MHz. clock
yields a broad pulse of 20.741 µs in duration. This tiny deviation will not cause a
problem for any High Definition television set.
To change the pixel clock frequency the encoder transmits and expects in
return, the CX25870’s PLL_INT and PLL_FRACT registers must be modified.
For 720p support with Character Clock Based Data Masters, change the
PLL_INT[5:0] bit field from 21 hex (for 74.25 MHz.) to 20hex for 74.1600 MHz.
operation. Furthermore, reduce the 2-byte wide PLL_FRACT[15:0] from 0000
hex (for 74.25 MHz.) to F5C3 hex for 74.1600 MHz. operation. This reduction in
the PLL_INT and PLL_FRACT registers will ensure the encoder transmits the
modified 720p clock of 74.1600 MHz. to the data master through CLKO and
expects to receive data at this frequency coming back (via CLKI). This step must
be done to render 720p via Character Clock Based Data Masters with the
CX25870. Programming the data master’s HTOTAL register to 1648 is vital as
well. Modifying the CX25870’s H_CLKI register to 1648 decimal is optional
because this register will have no effect while the encoder is outputting HDTV.
In summary, for data masters which are character clock based with 8 and 9
pixel clocks per character and wish to support the 720p resolution, slow down the
pixel input clock frequency (CLKI) by 90 kHz. to 74.1600 MHz and compensate
by reducing HTOTAL by 2 pixels per line to 1648 pixels.
100381B
Conexant
E-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
