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CX25870 参数 Datasheet PDF下载

CX25870图片预览
型号: CX25870
PDF下载: 下载PDF文件 查看货源
内容描述: 视频编码器与自适应闪烁过滤和HDTV输出 [Video Encoder with Adaptive Flicker Filtering and HDTV Output]
分类和应用: 电视编码器
文件页数/大小: 291 页 / 3791 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX25870/871  
Appendix C Autoconfiguration Mode Register Values and Details  
Flicker-Free Video Encoder with Ultrascale Technology  
Table C-6. CX25870/871 Register Values for Autoconfiguration Modes 27–30 (2 of 2)  
Autoconfiguration Mode #  
27  
28(5)  
29(5)  
30  
0x8E  
0x90  
13  
06  
13  
F0  
31  
00  
40  
00  
00  
8C  
0A  
E5  
76  
C1  
89  
9A  
1F  
7C  
F0  
21  
13  
38  
16  
20  
35  
00  
40  
00  
00  
8C  
24  
F0  
59  
CF  
93  
A4  
CB  
8A  
09  
2A  
04  
B1  
73  
00  
3F  
9A  
A9  
5D  
74  
1D  
0A  
E5  
74  
77  
43  
85  
2F  
A1  
BD  
14  
0x92  
0x94  
0x96  
0x98  
0x9A  
0x9C  
0x9E  
0xA0  
0xA2  
0xA4  
0xA6  
0xA8  
0xAA  
0xAC  
0xAE  
0xB0  
0xB2  
0xB4  
NOTE(S):  
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an  
autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input  
mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel  
input mode immediately before initiating a write to the CONFIG[5:0] bits.  
2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration  
command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately  
before initiating a write to the CONFIG[5:0] bits.  
3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an  
autoconfiguration command.  
4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock  
controllers.  
(5)  
The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29.  
6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was  
utilized instead.  
7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the  
14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz  
crystal.  
100381B  
Conexant  
C-13  
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