CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-8. CX25870/871 Register Values for Autoconfiguration Modes 37–42 (2 of 2)
Autoconfiguration Mode #
37
38
39
40
41
42
0x8C
0x8E
0F
0B
8A
68
E0
36
48
51
E4
B8
0D
24
F0
58
81
48
8C
3D
E7
C2
24
43
0C
25
7D
58
3B
11
A1
46
17
19
0A
E5
74
77
43
85
21
0B
59
18
83
03
20
7A
58
3B
F6
98
8E
E3
10
24
F0
57
7F
48
8C
E1
5B
DE
1D
43
0C
02
69
58
3B
EF
5E
00
00
18
0A
E5
74
78
43
85
17
5D
74
19
C5
1F
3B
41
C8
31
21
80
00
00
0E
24
F0
58
81
48
8C
D3
2D
08
24
7F
04
F7
96
00
3F
DE
AD
E8
A2
1F
0A
E5
74
77
43
85
C2
72
4F
13
0x90
0x92
0x94
0x96
0x98
0x9A
0x9C
0x9E
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xAC
0xAE
0xB0
0xB2
0xB4
NOTE(S):
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an
autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input
mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel
input mode immediately before initiating a write to the CONFIG[5:0] bits.
2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration
command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately
before initiating a write to the CONFIG[5:0] bits.
3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an
autoconfiguration command.
4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock
controllers.
5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29.
6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was
utilized instead.
7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the
14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz
crystal.
100381B
Conexant
C-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
