CX11656 HomePlug 1.0 PHY Data Sheet
GPSI_TXD: GPSI_TXD contains the data to be transmitted and transitions
synchronously with respect to GPSI_TXCLK. It is generally assumed that the data will
contain a properly formatted Ethernet frame (see MII Frame Structure above). That is, the
first bits on GPSI_TXD correspond to the preamble, followed by Start Frame Delimiter
(SFD) and the rest of the Ethernet frame (DA, SA, length/type, data, CRC).
3.2.2
SPI Slave Port Interface
The CX11656 implements a SPI Slave port that when connected to an external host
controller containing a SPI Master, can be used to control access to the two configuration
registers. The SPI Slave port uses a 16- bit control field (MSb first) consisting of a 6-bit
command field, a 5-bit reserved field, and a 5-bit address field to control access to the
two configuration registers detailed above (Table 3-5). Following the control field, the
16-bit register contents are written or read based on the command field.
Table 3-5. SPI Slave Command Summary
Register function
Control Field
15 14 13 12 11 10
9
87
6
5
4
3
2
1
0
Command Field
Reserved Field
Address Field
5
4
L
3
L
2
L
1
H
0
L
4
3
L
2
L
1
L
0
L
4
L
3
L
2
L
1
L
0
L
Write PLCSR0
L
H
(Control Register)
Read PLCSR0
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
(Control Register)
Write PLCSR1 (Status
Register)
Read PLCSR1 (Status
Register)
H
CX11656 SPECIFICATION
3.2.2.1
SPI Slave Port Signal Timing
SPI Slave Port timing is illustrated in Figure 3-18.
102069A
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