CX11656 HomePlug 1.0 PHY Data Sheet
Figure 3-18. SPI Slave Port Timing
tSPIS_LOW
tSPIS_HIGH
SPIS_CLK
SPIS_DI
tSPIS_SU
MSB IN
BITS 6-1
LSB IN
tSPIS_H
SPIS_DO
BITS 6-1
MSB OUT
LSB OUT
tSPIS_CSLAG
tSPIS_SDOSV
SPIS_CS_N
tSPIS_CSLEAD
102069_022
3.2.2.2
SPI Slave Port DC Characteristics
The SPI Slave Port DC characteristics are listed in Table 3-6.
Table 3-6. SPI Slave Port DC Characteristics
Parameter
Symbol
tSPIS_F
tSPIS_HIGH
tSPIS_LOW
tSPIS_SDOVD
tSPIS_CSLEAD
tSPIS_CSLAG
tSPIS_SU
Parameter Name
Test Condition
Min
Max
Unit
2.1
MHz
ns
ns
ns
ns
ns
ns
ns
SPIS_SCLK Frequency
SPIS_SCLK High Time
SPIS_SCLK Low Time
SPIS_SDO Valid Output Delay from SPIS_SCLK
SPIS_CS Lead to SPIS_SCLK
SPIS_CS Lag from SPIS_SCLK
SPIS_SDI Setup Time to SPIS_SCLK
SPIS_SDI Hold Time to SPIS_SCLK
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
400
400
0
500
1500
200
200
500
tSPIS_H
3.3
Clocks
The CX11656 runs from a single 100 MHz oscillator input and generates a 50 MHz clock
to feed the ADC, a 50 MHz clock to feed the DAC, the 25 MHz MII clock, and the 10
MHz GPSI clock. The 100 MHz clock input directly feeds the clock distribution network
that clocks up to 60% of the digital logic.
Note: Both CLKIN and CLKOUT connect directly to the +1.8 V core of the IC and do
not connect to the +3.3 V I/O ring. Therefore these pins are not +3.3 V or +5 V
tolerant.
The oscillator must have 25 PPM RMS maximum tolerance including initial accuracy,
temperature/voltage range and 5 years of aging. This oscillator must have a symmetry no
worse than 40/60, jitter of 75 ps and 4 ns rise and fall time. The oscillator must be rated
over the desired temperature range and 10% voltage range. The CX11656 uses a crystal
input cell to receive the clock input.
3-16
Conexant Proprietary and Confidential Information
102069A
CONEXANT [ CONEXANT SYSTEMS, INC ]
