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CN8474AEPF 参数 Datasheet PDF下载

CN8474AEPF图片预览
型号: CN8474AEPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CN8478/CN8474A/CN8472A/CN8471A  
7.0 Electrical and Mechanical Specifications  
Multichannel Synchronous Communications Controller (MUSYCC™)  
7.2 Timing and Switching Specifications  
Table 7-8. PCI I/O Timing Parameters, 33 MHz PCI Clock  
Symbol  
Tval  
Parameter  
Min  
Max  
11  
12  
13  
28  
Unit  
ns  
PCLK to Signal Valid Delay—Bused Signal(1, 2, 4)  
PCLK to Signal Valid Delay—Point To Point(1, 2)  
Float to Active Delay(3)  
2
2
Tval (ptp)  
Ton  
ns  
7
ns  
Active to Float Delay(3)  
Toff  
ns  
Input Setup Time to Clock—Bused Signal(2)  
Input Setup Time to Clock—Point To Point(2)  
Input Hold Time from Clock(5)  
Tds  
ns  
Tsu (ptp)  
Tdh  
10, 12  
0
ns  
ns  
NOTE(S):  
(1)  
Minimum and maximum times are evaluated at 80 pF equivalent load. Actual test capacitance may vary, and results should  
be correlated to these specifications.  
REQ* and GNT* are the only point-to-point signals and have different output valid delay and input setup times than bused  
signals. GNT* has a setup of 10; REQ* has a setup of 12.  
For purposes of active/float timing measurements, the high-Z or off state is when the total current delivered through the  
component pin is less than or equal to the leakage current specification at 80 pF equivalent load.  
TVAL = 17 ns max for INTA.  
(2)  
(3)  
(4)  
(5)  
Tdh = 0.5 ns min for GNT, IDSEL, and IRDY.  
Table 7-9. PCI I/O Timing Parameters, 66 MHz PCI Clock  
Symbol  
Tval  
Parameter  
Min  
2
Max  
6
Units  
ns  
PCLK to Signal Valid Delay—Bused Signal(1, 2)  
PCLK to Signal Valid Delay—Point To Point(1, 2)  
Float to Active Delay(3)  
Tval (ptp)  
Ton  
2
6
ns  
2
14  
ns  
Active to Float Delay(3)  
Toff  
3
ns  
Input Setup Time to Clock—Bused Signal(2)  
Input Setup Time to Clock—Point To Point(2)  
Input Hold Time from Clock  
Tds  
ns  
Tsu (ptp)  
Tdh  
5
ns  
0
ns  
NOTE(S):  
(1)  
Minimum and maximum times are evaluated at 80 pF equivalent load. Actual test capacitance may vary, and results should  
be correlated to these specifications.  
REQ* and GNT* are the only point-to-point signals and have different output valid delay and input setup times than bused  
signals. GNT* has a setup of 10; REQ* has a setup of 12.  
For purposes of active/float timing measurements, the high-Z or off state is when the total current delivered through the  
component pin is less than or equal to the leakage current specification at 80 pF equivalent load.  
(2)  
(3)  
100660E  
Conexant  
7-7  
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