CN8478/CN8474A/CN8472A/CN8471A
7.0 Electrical and Mechanical Specifications
Multichannel Synchronous Communications Controller (MUSYCC™)
7.2 Timing and Switching Specifications
7.2.3 Expansion Bus (EBUS) Timing and Switching Characteristic
The EBUS timing is derived from the PCI clock (PCLK) input to MUSYCC. The
ECLK output is either one-half of the PCI clock (M66EN = 1) or the same as the
PCI clock (M66EN = 0); the ECLK and PCLK relationship is shown in
Figures 7-8 and 7-9.
The EBUS I/O timing characteristics are identical to the PCI I/O timing
characteristics.
The EBUS clock waveform characteristics are identical to the PCI clock
waveform characteristics (refer to Tables 7-11 through 7-13 and Figures 7-10
through 7-12).
Figure 7-8. ECLK to PCLK Relationship (M66EN = 0)
V
V
th
PCLK
ECLK
V
test
tl
V
test
V
tl
T
de
8478_031
Figure 7-9. ECLK to PCKL Relationship (M66EN = 1)
PCLK
ECLK
T
de
8478_031a
Table 7-11. EBUS Reset Parameters
Symbol
Toff
Parameter
Min
Max
Units
Active to Inactive Delay(1)
—
30
ns
NOTE(S):
(1)
For purposes of active/float timing measurements, the high-Z or off state is when the total current delivered through the
component pin is less than or equal to the leakage current specification.
100660E
Conexant
7-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
