7.0 Electrical and Mechanical Specifications
CN8478/CN8474A/CN8472A/CN8471A
7.2 Timing and Switching Specifications
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 7-4. PCI Interface DC Specifications (2 of 2)
Symbol
Vol
Parameter
Output Low Voltage(3)
Condition
Min
—
—
5
Max
0.1 VDD
10
Unit
V
Iout = 1500 µA
Input Pin Capacitance(4)
CLK Pin Capacitance
Cin
—
—
—
—
pF
pF
pF
nH
Cclk
12
IDSEL Pin Capacitance(5)
Pin Inductance(6)
CIDSEL
Lpin
—
—
8
20
NOTE(S):
(1)
Guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network.
Applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this
input voltage.
Input leakage currents include hi-Z output leakage for all bidirectional buffers with three-state outputs.
Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter
includes FRAME*, TRDY*, IRDY*, DEVSEL*, STPP*, SERR*, and PERR*
Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only
devices, which could be up to 16 pF, in order to accommodate PGA packaging. This would mean, in general, that components
for expansion boards would need to use alternatives to ceramic PGA packaging – i.e., PQFP, SGA, etc.
Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
(2)
(3)
(4)
(5)
(6)
This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.
Table 7-5. PCI Clock (PCLK) Waveform Parameters, 33 MHz PCI Clock
Symbol
Tcyc
Parameter
Clock Cycle Time(1)
Min
30
Max
—
—
—
4
Unit
ns
Thigh
Tlow
–
Clock High Time
Clock Low Time
11
ns
11
ns
Clock Slew Rate(2)
1
V/ns
V
Vptp
Peak-to-Peak Voltage
0.4 Vdd
—
NOTE(S):
(1)
MUSYCC works with any clock frequency between DC and 66 MHz, nominally. The clock frequency can be changed at any
time during operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times
are not violated. The clock can only be stopped in a low state.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.
(2)
7-4
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
