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CN8474AEPF 参数 Datasheet PDF下载

CN8474AEPF图片预览
型号: CN8474AEPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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6.0 Basic Operation  
CN8478/CN8474A/CN8472A/CN8471A  
6.2 Configuration  
Multichannel Synchronous Communications Controller (MUSYCC™)  
6.2 Configuration  
A sequence of hierarchical initializations must occur after resets. The levels of  
hierarchy are as follows:  
1. PCI Configuration—only after hardware reset  
2. Global Configuration  
3. Interrupt Queue Configuration  
4. Channel Group(s) Configuration  
6.2.1 PCI Configuration  
After power-up or a PCI reset sequence, MUSYCC enters a holding pattern,  
waiting for PCI configuration cycles directed specifically for MUSYCC at the  
PCI bus and PCI slot MUSYCC resides in.  
PCI configuration involves PCI read and write cycles initiated by the host and  
performed by a host-bus-to-PCI-bus bridge device. The cycles are executed at the  
hardware signal level by the bridge device. The bridge device polls all possible  
slots on the bus it controls for a PCI device and then iteratively reads the  
configuration space for all supported functions on each device. All information  
from the basic configuration sequence is forwarded to the system controller or  
host processor controlling the bridge device.  
During PCI configuration, the host can perform the following configuration  
for MUSYCCs Function 0, HDLC Network Controller function:  
Read PCI configuration space (Device Identification, Vendor  
Identification, Class Code, and Revision Identification).  
Allocate 1 MB system memory range and assign the Base Address register  
using this memory range.  
Allow fast back-to-back transactions.  
Enable PCI system error signal line, SERR*.  
Allow response for PCI parity error detection.  
Allow PCI bus-master mode.  
Allow PCI bus-slave mode.  
Assign latency.  
Assign interrupt line routing.  
During PCI configuration, the host can perform the following configuration  
for MUSYCCs Function 1, PCI to EBUS bridge:  
Read PCI configuration space (Device Identification, Vendor  
Identification, Class Code, and Revision Identification).  
Allocate 1 MB system memory range and assign the Base Address register  
using this memory range.  
Allow response for PCI parity error detection.  
Assign latency.  
Assign interrupt line routing.  
6-4  
Conexant  
100660E