1.0 Product Description
CN8223
1.9 Logic Diagram
ATM Transmitter/Receiver with UTOPIA Interface
Figure 1-11. CN8223 Logic Diagram
Line Framer/PHY
Interface
31
10
11,12
20,21
15–19,
154,155
22,25
30
23,24
32
Receive Clock Input
Receive Clock In PECL
Receive Serial In PECL
I
I
I
RXCKI
TCLKO
Transmit Clock Output
O
33–36,
42,43,
56–58
RXCKI_HS
RXIN_HS
TXOUT[8:0]
O Transmit Outputs
I
I
Receive Input
Transmit Clock Input
RXIN[8:0]
TXCKI
TXCKI_HS
TXIN
28,29
TCLKO_HS
TXOUT_HS
LOCD
O Transmit Clock Out PECL
Transmit Serial Out PECL
O
38,39
122
Transmit Clock In PECL
Transmit Input
I
I
Loss of Cell Delineation
O
Framing Overhead
Interface
2–5,
Transmit Overhead
Bus In
44–51
I
TXOVH[7:0]
RXOVH[7:0] 156–159
Receive Overhead Bus Out
Receive Overhead Markers
O
O
8,9
6,7
RMRKR[1:0]
ROVH_CLK[1:0]
O Receive Overhead Clocks
55
52
TOVH_CLK
TMRKR
Transmit Overhead Clock
Transmit Overhead Marker
O
O
UTOPIA/FIFO
Interface
98–105,
143–145,
108
FDAT_OUT[8:0] 148–153
O FIFO Data Bus Out
FIFO Data Bus In I
FDAT_IN[8:0]
124–132,
135–142
109–116
FCTRL_IN[7:0]
I
FIFO Control Input
FCTRL_OUT[16:0]
O FIFO Control Outputs
37
97
96
94
95
92
I
I
I
I
I
SEL8BIT
PRCLK
CS~
AS~
W/R~
OE~
8/16-Bit Mode Select
Processor Clock
Chip Select
Address Strobe
Write/Read Control
63
64
O FEAC/HDLC Interrupt
O Status/Counter Interrupt
DL_INT
STAT_INT
Microprocessor
Output Enable I
Interface
65,
68–79,
82–84
Processor Data Bus
Address Bus
D[15:0]
A[7:1]
I/O
I
85–91
Clock and Control
62
61
123
8KCKI
8 kHz Clock Input
One-Second Clock Sync I
I
ONESECI
RCV_HLD
NTEST
I
I
I
Receiver Hold Input
Test Input
60
ONESECO
O One-Second Output
59
117,119
118
TEST1, TEST3
RESET
Test Inputs
Reset I
I = Input, O = Output
1-18
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
