Bt860/861
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Multiport YCrCb to NTSC/PAL /SECAM
Register 3C
Default
Value
Register
3C
D7
D6
D5
D4
D3
D2
D1
D0
10
VIDCLK_EDGE YDELAY[0]
XL_MDSEL[1:0]
XL_SATEN
FIL_SEL
SCART_SEL
VIDCLK_EDGE
VIDCLK EDGE Sample Select
0 = VID[7:0], VIDHACT, VIDVALT, VIDFIELD, VIDVALID are sampled on the rising edge of
the VIDCLK.
1 = VID[7:0], VIDHACT, VIDVALT, VIDFIELD, VIDVALID are sampled on the falling edge of
the VIDCLK.
YDELAY[0]
Luma Delay is System Clock Counts for CVBS_DLY Outputs.
The MSBs for YDELAY are located in register 18.
0 = No delay.
1 = One system clock delay (1/2 pixel).
XL_MDSEL[1:0]
Accelerated Locking Mode Select
00 = Rapid frequency adjustment.
01 = Moderate frequency adjustment.
11 = Slow frequency adjustment.
XL_SATEN
FIL_SEL
Accelerated Locking Saturation Enable
00 = Disable accelerated locking saturation limit.
01 = Enable a saturation limit for the initial internal PLL adjustment of the accelerated
locking sequence. The limit value is determined by the XL_SAT register field (73[3:0]).
Filters Select
0 = Enable peaking filters.
1 = Enable reduction filters.
See PKFIL_SEL register bit description.
SCART_SEL
Scart Selection Options
00 = Disable SCART functionality on ALTADDR pin.
01 = ALTDDR pin is VBLANK signal.
10 = ALTDDR pin is composite sync signal.
11 = ALTDDR pin is composite blank signal.
These signals are synchronized with the DAC outputs. See Figure 3-15.
Register 40–41
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
40
80
80
XDSB1[7:0]
XDSB2[7:0]
41
XDSB1[7:0]
First Byte of Extended Data Services Information
Data is encoded LSB first.
XDSB2[7:0]
Second Byte of Extended Data Services Information
Data is encoded LSB first.
D860DSA
Conexant
5-31
CONEXANT [ CONEXANT SYSTEMS, INC ]
