5.0 Serial Programming Interface and Registers
5.2 Internal Registers
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-2. Register Bit Map (3 of 4)
Sub
addr
Default
Values(1)
D7
D6
D5
D4
D3
D2
D1
D0
Reserved(4)
36
37
04
00
00
50
FA
00
10
00
80
80
80
80
4A
01
8C
09
00
44
—
—
—
39
01
07
00
00
00
00
00
00
00
00
00
DB_MIN[10:8]
Y_OFF[7:0]
38
PHASE_OFF[7:0]
39
ALPHA_LUT_1[3:0]
ALPHA_LUT_3[3:0]
HUE_ADJUST[7:0]
ALPHA_LUT_0[3:0]
ALPHA_LUT_2[3:0]
3A
3B
3C
3D–3F
40
VIDCLK_EDGE
Reserved
YDELAY[0] XL_MDSEL[1:0]
XL_SATEN FIL_SEL
SCART_SEL[1:0]
XDSB1[7:0]
XDSB2[7:0]
CCB1[7:0]
41
42
43
CCB2[7:0]
44
CCSTART[7:0]
Reserved(4)
CCADD[7:0]
Reserved(4)
Reserved(4)
XDSSEL[3:0]
EWSSF2
45
CCSTART[8]
ECC
46
47
CCADD[11:8]
ECCGATE
48
EXDS
49
CCSEL[3:0]
WSDAT[4:1]
Reserved(4)
4A
4B
4C
4D
4E
4F
50
EWSSF1
SQUARE
WSDAT[12:5]
WSDAT[20:13]
TTXHS[7:0]
Reserved(4)
TTXHE[7:0]
Reserved(4)
TTXBF1[7:0]
Reserved(4)
TTXEF1[7:0]
Reserved(4)
TTXXBF2[7:0]
Reserved(4)
TTXEF2[7:0]
Reserved(4)
TTXHS[10:8]
TTXHE[10:8]
51
52
TTXBF1[8]
TTXEF1[8]
TTXXBF2[8]
TTXEF2[8]
53
54
55
56
57
58
5-6
Conexant
D860DSA