5.0 Serial Programming Interface and Registers
5.1 Serial Interface
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Every data word put onto the SID line must be 8 bits long (MSB first),
followed by an acknowledge bit, generated by the receiving device. Each data
transfer is initiated with a start condition and ended with a stop condition. The
first byte after a start condition is always the slave address byte. If this is the
device address, the device generates an acknowledge signal by pulling the SID
line low during the ninth clock pulse.
The eighth bit of the address byte is the read/write* bit (high = read from the
addressed device, low = write to the addressed device). Data bytes are always
acknowledged during the ninth clock pulse by the addressed device.
NOTE: During the acknowledge period, the master device must leave the SID line
high.
Premature termination of the data transfer is allowed by generating a stop
condition at any time. When this happens, the Bt860/861 remains in the state
defined by the last complete data byte transmitted, and any master acknowledge
subsequent to reading the chip ID (subaddress 0x89) is ignored.
5.1.1 Device Address
The device address is configurable by the state of the ALTADDR pin at reset. If
SCART functionality is not desired, the ALTADDR pin may be tied directly to
power or ground to configure this address. Otherwise, the address should be
configured through a soft-tie resistor to power or ground. Table 5-1 lists how the
ALTADDR pin configures the device address.
Table 5-1. Serial Address Configuration
Device Address
Byte for Writes
Device Address
Byte for Reads
ALTADDR
Device Address
0
1
7’b1000101
7’b1000100
0x8A
0x88
0x8B
0x89
5.1.2 Writing Data
A write transaction involves sending the device address byte with the read/write*
bit low, and following it with one or more bytes. The first byte following the
device address byte is always assumed to be a register subaddress, and sets an
internal register subaddress pointer. This address is an 8-bit quantity, thus
allowing the addressing of up to 256 byte-wide registers. If a second byte follows
the device address byte, it is assumed to be the write data for the register indexed
in the first byte. Any subsequent bytes are assumed to be write data for registers
whose address follows in ascending order, as the internal subaddress pointer is
incremented at the completion of each register write. The state of this internal
address pointer upon exiting a write transaction is used for any read transactions
that follow.
Figure 5-2 illustrates a typical register write sequence.
1. Master transmits the device address with the read/write* bit low.
2. Master transmits the desired register subaddress.
3. Master transmits the register write data byte.
4. Subsequent registers are written until a stop condition is detected.
5-2
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
