Bt860/861
3.0 Digital Processing and Functionality
3.2 Effects
Multiport YCrCb to NTSC/PAL /SECAM
3.2.11 Special SCART Signals
At power-up, the ALTADDR pin is sampled to determine the Bt860/861’s serial
programming address. At all other times the SCART_SEL (3C[1:0]) register field
determines its function. Setting the SCART_SEL register field to 00 will
three-state the ALTADDR pin; setting it to 01 produces a Vertical Blank signal on
the ALTADDR pin; setting it to 10 produces a Composite Sync signal on the
ALTADDR pin; and setting it to 11 produces a Composite Blank signal on the
ALTADDR pin. These signals are 3.3 V TTL signals that are aligned with the
outgoing video, as illustrated in Figure 3-15.
Figure 3-15. SCART Function on ALTADDR Pin
Composite
Video
SCART _SEL [1:0]
ALTADDR Pin
(Vertical Blank)
01
ALTADDR Pin
(Composite Sync)
10
11
ALTADDR Pin
(Composite Blank)
861_034a
3.2.12 Output Connection Status
DAC connection status can be checked automatically or manually. When the
AUTO_CHECK (1B[2]) register bit is set to 1, the connection status of the DACs
is automatically checked once per frame. When the AUTO_CHECK register bit
is set to 0 (default), setting the CHECK_STAT register bit to 1 initiates a single
check of the DAC connection status. This bit is automatically cleared. The
connection status of the DAC is then represented on the MONSTAT_A through
MONSTAT_F register bits (01[7:2]). A 1 indicates that a properly terminated
load has been detected on that DAC. Because the Bt860/861 checks for a double
terminated load (combined 37.5 Ω), improper termination causes the load to be
misrepresented. The DAC output must be enabled for proper sensing.
D860DSA
Conexant
3-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
