欢迎访问ic37.com |
会员登录 免费注册
发布采购

BT861KRF 参数 Datasheet PDF下载

BT861KRF图片预览
型号: BT861KRF
PDF下载: 下载PDF文件 查看货源
内容描述: 多端口的YCrCb到NTSC / PAL / SECAM数字视频编码器 [Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder]
分类和应用: 商用集成电路编码器
文件页数/大小: 111 页 / 1232 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
 浏览型号BT861KRF的Datasheet PDF文件第52页浏览型号BT861KRF的Datasheet PDF文件第53页浏览型号BT861KRF的Datasheet PDF文件第54页浏览型号BT861KRF的Datasheet PDF文件第55页浏览型号BT861KRF的Datasheet PDF文件第57页浏览型号BT861KRF的Datasheet PDF文件第58页浏览型号BT861KRF的Datasheet PDF文件第59页浏览型号BT861KRF的Datasheet PDF文件第60页  
3.0 Digital Processing and Functionality  
3.2 Effects  
Bt860/861  
Multiport YCrCb to NTSC/PAL /SECAM  
3.2.15.1 Teletext Timing  
Mode 1  
Setting register bit TXRM to 1 puts the Bt860/861 in Teletext timing mode 1. In  
this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin is  
configured as the Teletext timing clock. The Teletext clock timing is fixed  
internally and has an average frequency of 6.9375 MHz. The Teletext timing clock  
does not have a consistent period, because it is derived from the system clock,  
which is not evenly divisible by 6.9375 MHz. The clock period varies from 3–4  
system clocks for ITU-R BT.601 timing, and 4–5 system clocks for square pixel  
timing. Teletext data is latched on the falling edge of this clock. The first rising  
edge occurs 335 system clocks after falling HSYNC* for ITU-R BT.601  
timing (27 MHz).  
3.2.15.2 Teletext Timing  
Mode 2  
Setting register bit TXRM to 0 puts the Bt860/861 in Teletext timing mode 2. In  
this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin  
is configured as the Teletext data request line. In this mode, the same Teletext  
timing clock as in mode 1 is fixed internally. The rising edge of the TTXREQ  
signal means start transmitting data, and the falling edge means stop transmitting  
data. The 11-bit register fields TTXHS[10:0] and TTXHE[10:0] control the  
placement of the rising and falling edges. Each LSB represents a one system  
clock count (27 MHz or 29.5 MHz) increment. When the system clock is 27  
MHz, there is a 4 clock offset between the falling edge of HSYNC* and the rising  
or falling edge of the TTXREQ request signal. For example, a value of 0x001 on  
either register places the respective edge at 5 clocks from falling HSYNC*. The  
register values of TTXHS and TTXHE cannot be zero, equal to, or greater than  
the total number of system clocks per line.  
The internal Teletext timing clock can be externally reproduced using a P:Q  
ratio counter, such as the one conceptualized in Figure 3-17. Table 3-10 lists  
appropriate values for ITU-R BT.601 and square pixel timing.  
Figure 3-17. P:Q Ratio Counter Block Diagram  
ADDER  
MODULO  
Q
REGISTER  
A
SUM  
CO  
P
B
CLK  
RSTN  
ENABLE_TTX_CLK  
TELETEXT CLOCK  
Q
D
CLK  
861_004  
Table 3-10. P:Q Ratio Counter Values  
CLK  
Pixel Rate  
P
Q
27 MHz  
13.5 MHz  
37  
144  
ITU-R BT.601  
29.5 MHz  
14.75 MHz  
111  
472  
Square Pixel  
3-26  
Conexant  
D860DSA  
 复制成功!