2.0 Circuit Description
2.8 Transmitter
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Patterns are generated in accordance with ITU–T O.150 (10/92), O.151
(10/92), and O.152 (10/92). Enabling ZLIMIT modifies the inserted pattern by
limiting the number of consecutive 0s. For the 2E11-1 or 2E15-1 PRBS patterns,
8 or more 0s does not occur with ZLIMIT enabled. For the 2E20-1 or 2E23-1
PRBS patterns, 15 or more 0s will not occur with ZLIMIT enabled.
NOTE: The QRSS pattern is a 2E20-1 PRBS with ZLIMIT enabled. This function
is performed according to ANSI T1.403 and ITU–T O.151 (10/92).
Frame bit positions can be preserved in the output pattern by enabling
FRAMED. In T1 mode, this prevents the test pattern from overwriting the frame
bit which occurs every 193 bits. In E1 mode with FRAMED enabled, the test
pattern does not overwrite time slot 0 data (FAS and NFAS words) and time slot
16 (CAS signalling word) if CAS framing is also selected. CAS framing is
selected by setting TFRAME[3] to 1 in the Transmit Configuration register
[TCR0; addr 070]. The test pattern is stopped during these bit periods according
to ITU-T O.151, (10/92). If FRAMED is disabled, the test pattern is transmitted in
all time slots.
2.8.6 Transmit Error Insertion
The Transmit Error Insert register [TERROR; addr 073] controls error insertion
during pattern generation. Writing 1 to a TERROR bit injects a single occurrence
of the respective error on TPOSO/TNEGO and XTIP/XRING outputs. Writing a
0 has no effect. Multiple transmit errors can be generated simultaneously.
Periodic or random bit error rates can also be emulated by software control of the
error control bit.
NOTE: Injected errors affect the data sent during a Framer or Analog Loopback
[FLOOP or ALOOP; addr 014].
Line Code Violations (LCV) are inserted via the TVERR bit of the TERROR
register. In T1 mode, if TVERR is set, a BPV is inserted between two consecutive
ones. TVERR is latched until the BPV is inserted into the transmit data stream,
and then it is cleared. In E1 mode with HDB3 selected, two consecutive BPVs of
the same polarity are inserted. This is registered as a single LCV for the receiving
E1 equipment.
Ft, FPS, and FAS bit errors are inserted using the TFERR bit in the TERROR
register. TFERR commands a logical inversion of the next frame bit transmitted.
CRC4 (E1) and CRC6 (T1) bit errors are inserted using the TCERR bit in the
TERROR register. TCERR commands a logical inversion of the next CRC bit
transmitted.
Change of Frame Alignments (COFA) are controlled by the TCOFA and
BSLIP bits in the TERROR register. TCOFA commands a 1-bit shift in the
location of the transmit frame alignment by deleting (or inserting) a 1-bit position
from the transmit frame. During E1 modes, BSLIP determines which direction
the bit slip occurs. In T1 modes, only 1-bit deletion is provided. Note that TCOFA
alters extraction rate of data from transmit slip buffer; thus, repeated TCOFAs
eventually cause a controlled frame slip where 1 frame of data is repeated
(T1/BSLIP = 0), or where 1 frame of data is deleted (BSLIP = 1).
PRBS test pattern errors are inserted by TBERR in the TERROR register.
TBERR commands a single PRBS error by logically inverting the next PRBS
generator output bit.
2-64
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
