Bt8370/8375/8376
2.0 Circuit Description
2.8 Transmitter
Fully Integrated T1/E1 Framer and Line Interface
The insertion of E1 Multiframe Yellow Alarm is controlled by INS_MYEL.
E1 Multiframe Yellow Alarm is inserted only when INS_MYEL is set.
Multiframe Yellow Alarm generation can be initiated manually or automatically.
Manual insertion of Multiframe Yellow Alarm is controlled by TMYEL.
Setting this bit unconditionally overwrites the Multiframe Yellow Alarm signal
bit in the transmitted data stream.
Automatic insertion of Multiframe Yellow Alarm is controlled by
AUTO_MYEL in the TALM register. When set, the AUTO_MYEL mode sends a
yellow alarm for the duration of a Receive Loss of CAS Multiframe Alignment
[SRED; addr 049].
2.8.4.3 CRC Generation
The CRC generation circuitry computes the value of the CRC-6 code in T1 mode
or the CRC-4 code in E1 mode. Once computed, it is inserted into the appropriate
position of the transmitted data stream. CRC overwrite is enabled by the
INS_CRC bit in Transmit Frame Format [TFRM; addr 072].
If the transmit frame format is configured as ESF, and the INS_CRC bit is
active, the 2 kbps CRC sequence is inserted. (The position of the CRC-6 bits is
shown in Table A-4, Extended Superframe Format).
If the transmit frame format is configured as E1 and the INS_CRC bit is
active, the 4 kbps CRC sequence is inserted. (The position of the CRC-4 bits is
shown in Table A-6, ITU–T CEPT Frame Format Time Slot 0-Bit Allocations.)
2.8.4.4 Far-End Block
Error Generation
The Far-End Block Error (FEBE) generation circuitry inserts FEBE bits
automatically or manually. Automatic FEBE generation is enabled by the INS_FE
bit in TFRM. If the transmit frame format is configured as E1 and the INS_FE bit
is active, a FEBE is generated in response to an incoming CRC-4 error by setting
an E-bit of TS0 to 0. (Refer to Table A-7, IRSM CEPT Frame Format Time Slot
0-Bit Allocations for the location of the E-bits within the E1 frame.)
Manual FEBE generation is enabled by the TFEBE bit of the Transmit Manual
Sa-Byte/FEBE Configuration register [TMAN; addr 074]. If the transmit frame
format is configured as E1 and the TFEBE bit is active, the FEBE bits are
supplied by the processor in FEBE_I and FEBE_II bits [addr 074].
2.8.5 Test Pattern Generator
The transmit test pattern generation circuitry overwrites the transmit data with
various test patterns and permits logical and frame-bit error insertion. This feature
is particularly useful for system diagnostics, production testing, and test
equipment applications. The test pattern can be a framed or unframed PRBS
pattern. The PRBS patterns available include 2E11-1, 2E15-1, 2E20-1, and
2E23-1. Each pattern can optionally include Zero Code Suppression (ZCS). Error
insertion includes LCV, BPV, Ft, CRC4, CRC6, COFA, PRBS, Fs, MFAS, and
CAS.
The Transmit Test Pattern Configuration register [TPATT; addr 076] controls
the test pattern insertion circuit. TPATT controls the PRBS pattern (TPATT[1:0])
bits), ZCS setting (ZLIMIT bit), T1/E1 framing (FRAMED bit), and Starting and
Stopping transmission (TPSTART bit).
N8370DSE
Conexant
2-63
CONEXANT [ CONEXANT SYSTEMS, INC ]
