Bt8370/8375/8376
2.0 Circuit Description
2.3 Jitter Attenuator
Fully Integrated T1/E1 Framer and Line Interface
2.3 Jitter Attenuator
The Jitter Attenuator (JAT), illustrated in Figure 2-8, attenuates jitter in the
receive or transmit path, but not both simultaneously. In the receive configuration,
the line signal is recovered by the RLIU and is dejittered before it is decoded by
the RCVR. In the transmit configuration, the encoded signal from the transmit
block is dejittered before it is transmitted by the Transmit Line Interface Unit
(TLIU). The JAT receive/transmit configuration is done through the JDIR bit in
the Jitter Attenuator Configuration register [JAT_CR; addr 002]. The JAT can also
be completely disabled using the Jitter Attenuation (JEN) bit in the JAT_CR
register.
Figure 2-8. Jitter Attenuator Block Diagram
From RLIU
To RLIU
JCLK
(to CLAD)
RXCLK
Rin
Rout
RJAT
or
Depth
To JPHASE
TJAT
Tout
Tin
(from CMUX)
TXCLK
JCLK
To/From TLIU
N8370DSE
Conexant
2-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
