2.0 Circuit Description
Bt8370/8375/8376
2.2 Receive Line Interface Unit
Fully Integrated T1/E1 Framer and Line Interface
2.2.2 Clock Recovery
2.2.2.1 Phase Locked
Loop
The Receive Phase Locked Loop (RPLL) recovers the line rate clock from the
Data Slicer dual rail outputs. The RPLL generates a recovered clock that tracks
the jitter in the data from the Data Slicer, and sustains the data-to-clock phase
relationship in the absence of incoming pulses. Figure 2-7 illustrates the Receive
LIU’s input clock and data jitter tolerance.
Figure 2-7. Receive Input Jitter Tolerance
10000
Data Jitter
Tolerance
1000
138 UI
100
TR 62411 (T1)
Min. Tolerance
28 UI
Clock Jitter
Tolerance
10
1
G. 824 (T1)
Min. Tolerance
5 UI
Reg. G. 823 (E1)
Min. Tolerance
1.5 UI
0.35 UI
.22 UI
0.2UI
0.1UI
0.1
0.1
1
10
100
1000
10000
100000
Sine Wave Jitter Frequency (Hz) [Log Scale]
2-8
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
