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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Circuit Description  
Bt8370/8375/8376  
2.2 Receive Line Interface Unit  
Fully Integrated T1/E1 Framer and Line Interface  
2.2.2 Clock Recovery  
2.2.2.1 Phase Locked  
Loop  
The Receive Phase Locked Loop (RPLL) recovers the line rate clock from the  
Data Slicer dual rail outputs. The RPLL generates a recovered clock that tracks  
the jitter in the data from the Data Slicer, and sustains the data-to-clock phase  
relationship in the absence of incoming pulses. Figure 2-7 illustrates the Receive  
LIUs input clock and data jitter tolerance.  
Figure 2-7. Receive Input Jitter Tolerance  
10000  
Data Jitter  
Tolerance  
1000  
138 UI  
100  
TR 62411 (T1)  
Min. Tolerance  
28 UI  
Clock Jitter  
Tolerance  
10  
1
G. 824 (T1)  
Min. Tolerance  
5 UI  
Reg. G. 823 (E1)  
Min. Tolerance  
1.5 UI  
0.35 UI  
.22 UI  
0.2UI  
0.1UI  
0.1  
0.1  
1
10  
100  
1000  
10000  
100000  
Sine Wave Jitter Frequency (Hz) [Log Scale]  
2-8  
Conexant  
N8370DSE