2.0 Circuit Description
Bt8370/8375/8376
2.2 Receive Line Interface Unit
Fully Integrated T1/E1 Framer and Line Interface
Figure 2-5. RLIU Waveforms—Bipolar Input Signal
BPV
RTIP,
RRING
5
6
1
3
2
4
7
RXCLK
Throughput
3
BPV
6
1
5
RPOSO
RNEGO
7
2
4
If the RLIU functionality is not required, a bypass mode is provided [RDIGI;
addr 020]. If the RLIU is bypassed, the RTIP/RRING pins are ignored,
RPOSI/RNEGI P and N rail NRZ become inputs, and RCKI becomes the receive
timing source. Figure 2-6 illustrates the relationship between the RLIU P and N
rail NRZ data, the RLIU receive clock input, and the RCVR dual rail output.
Figure 2-6. RLIU Waveforms—P and N Rail Digital Input Signal
BPV
6
RPOSI
1
3
5
RNEGI
RCKI
2
4
7
Throughput
3
BPV
6
RPOSO
RNEGO
1
5
2
4
7
2-6
Conexant
N8370DSE