CN8223
1.0 Product Description
ATM Transmitter/Receiver with UTOPIA Interface
1.9 Logic Diagram
1.9 Logic Diagram
The CN8223 is a single CMOS integrated circuit, packaged in a 160-pin Plastic
Quad Flat Pack (PQFP). Figure 1-11 illustrates a CN8223 logic diagram. The line
framer/PHY interface consists of 33 pins. The framing overhead interface
consists of 22 pins. The FIFO interface consists of 18 data pins, 8 control inputs,
and 17 control outputs. The microprocessor interface consists of 8 clock and
control inputs, a 16-bit data bus, a 7-bit address bus, and 2 interrupt outputs.
Additionally, there are 11 power and 12 ground pins. Detailed pin descriptions are
given in Table 1-2.
Clock and control inputs consist of an external 8 kHz reference for the PLCP
at E3 and DS3 rates, a one-second input to synchronize status collection timing in
multiple-port applications, a “hold receiver” input that can externally disable cell
validation when an external framer loses frame or signal, three test inputs, and a
reset input. A one-second clock output is provided to allow synchronization of
status collection for multiple CN8223s or for CN8223s and framers. When a
single CN8223 is used, ONESECO should be connected to ONESECI. This
timing output is derived from the external 8 kHz reference clock input on 8KCKI.
An 8 kHz clock from the line receiver is available on RMRKR[1], pin 8.
NOTE: RMRKR[1] is not available in DS-3 direct cell mapping mode.
100046C
Conexant
1-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
