3.0 Registers
CN8223
3.7 Status Register Overview
ATM Transmitter/Receiver with UTOPIA Interface
3.7 Status Register Overview
There are four status registers, as defined in Table 3-11. Status registers are read-only. Some of the status
registers will be cleared when read, or have separate clear functions. The status indications can interrupt the
microprocessor if the corresponding bit is set in an Interrupt Enable Control register (Section 3.6). The interrupt
appears on the STAT_INT pin (pin 64).
Table 3-11. ATM Transmitter/Receiver Status Registers, Counters, and Data Link Control
Address
0x38
Name
Function
Line Framer/PHY Interrupt Status
LINE_STATUS
0x39
0x3A
0x3B
0x3C
EVENT_STATUS
OVFL_STATUS
CELL_STATUS
RXFEAC_VER
Event Interrupt Status—all bits are event driven
Counter Overflow Interrupt Status—all bits are event driven
Cell Counter Interrupt Status—all bits are event driven
Receive FEAC/Part Number/Version Number
3-28
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
