3.0 Registers
CN8223
3.6 Interrupt Enable Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.6 Interrupt Enable Control Registers
Four registers enable interrupts to appear on the STAT_INT interrupt output pin (pin 64). The EN_LINE_INT
(0x2D), EN_EVENT_INT (0x2E), EN_OVFL_INT (0x2F), and EN_CELL_INT (0x30) enable interrupts based
on the same bit positions in the corresponding STATUS registers. For example, the EN_LINE_INT register
enables the interrupts reported in the LINE_STATUS register.
0x2D—EN_LINE_INT (Enable Line Interrupts)
The EN_LINE_INT register is located at address 0x2D and enables interrupts for the LINE_STATUS register
(0x38). Setting a bit in EN_LINE_INT enables each interrupt condition to appear on STAT_INT.
Ext. Framer
(57 octet)
STS-1/STS-3c/
STM-1
Bit
Internal DS3
Internal G.751 E3
G.832 E3/E4
15
14
13
0
0
0
Line FEBE Error
0
One Second Count
Invalid FEBE
One Second Count
Invalid FEBE
One Second Count
Invalid FEBE
One Second Count
One Second Count
Signal Label
Mismatch
Payload Type
Mismatch
12
FEBE All-1s
PLCP FEBE Error
PLCP BIP Error
PLCP Frame Error
PLCP Yellow
PLCP LOF 2–3
PLCP LOF
PLCP OOF
x
FEBE All-1s
FEBE All-1s
PLCP FEBE Error
PLCP BIP Error
PLCP Frame Error
PLCP Yellow
PLCP LOF 2–3
PLCP LOF
Path FERF Error
Path FEBE Error
Summary BIP Error
Line FERF
MA FERF
MA FEBE
EM BIP Error
x
11
PLCP FEBE Error
PLCP BIP Error
PLCP Frame Error
PLCP Yellow/LOC
PLCP LOF 2–3
PLCP LOF
10
9
8
LOC
LOC
7
STS LOF 2–3
STS LOF
E3/E4 LOF 2–3
E3/E4 LOF
E3/E4 OOF
x
6
5
PLCP OOF/LOC
DS3 X bit Yellow
DS3 Idle Code
DS3 AIS
PLCP OOF
STS OOF
4
E3 A bit Yellow
x
Path Yellow
Path AIS
3
x
x
2
x
E3 AIS
Line AIS
E3/E4 AIS
x
1
x
DS3 OOF
E3 OOF
STS LOP
0
LOS (Input)
LOS (Input)
LOS (Input)
LOS (Input)
LOS (Input)
NOTE(S):
Notes: 1. EN_LINE_INT and LINE_STATUS have definitions that change with line interface mode.
2. “x” means content should be disregarded.
3-24
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
