3.0 Registers
CN8223
3.5 Receive Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
0x1D–0x24—HDR_MSKx_12, HDR_MSKx_34 (Receive Header Mask Register)
The Receive Header Mask registers for port x (where x can be 0 to 3) are located at addresses 0x1D–0x24.
These registers modify the ATM cell screen in the Receive Header Value register. Setting a bit in the Mask
register causes the corresponding bit in the received ATM cell header to be disregarded for screening. For
example, setting HDR_MSK0_12, bit 0 to 1 causes ATM cells to be accepted to port 0 with either 1 or 0 in the
octet 1, bit 0 position. Combinations of Receive Header Mask bits can select groups of ATM VPI/VCIs for each
of the four ports. The same cells can be sent to more than one port. Setting all bits to 1s overrides the contents of
the Receive Header Value register. HDR_MSKx Register addresses are listed in Table 3-10.
Table 3-10. HDR_MSKx Register Addresses
Address
Register Name
Description
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
HDR_MSK0_12
HDR_MSK0_34
HDR_MSK1_12
HDR_MSK1_34
HDR_MSK2_12
HDR_MSK2_34
HDR_MSK3_12
HDR_MSK3_34
Receive Port 0 ATM Header Mask—Octets 1, 2
Receive Port 0 ATM Header Mask—Octets 3, 4
Receive Port 1 ATM Header Mask—Octets 1, 2
Receive Port 1 ATM Header Mask—Octets 3, 4
Receive Port 2 ATM Header Mask—Octets 1, 2
Receive Port 2 ATM Header Mask—Octets 3, 4
Receive Port 3 ATM Header Mask—Octets 1, 2
Receive Port 3 ATM Header Mask—Octets 3, 4
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 1
Header Value—Octet 2
Receive Port X ATM Header Mask Value—Octet 1
Receive Port X ATM Header Mask Value—Octet 2
HDR_VAL0_34, HDR_VAL1_34, HDR_VAL2_34, HDR_VAL3_34
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 3
Header Value—Octet 4
Receive Port X ATM Header Mask Value—Octet 3
Receive Port X ATM Header Mask Value—Octet 4
3-22
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
