GMSK Modem Data Pump
Page 11 of 37
MX909A PRELIMINARY INFORMATION
4.4 The Programmer's View
The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers,
individual registers being selected by the A0 and A1 chip inputs:
A1
0
A0
0
Write to Modem
Data Buffer
Read from Modem
Data Buffer
0
1
Command Register
Control Register
Mode Register
Status Register
Data Quality Register
not used
1
0
1
1
4.4.1 Data Buffer
This is an 18-byte read/write buffer which is used to transfer data (as opposed to command, status, mode,
data quality and control information) between the modem and the host µC.
It appears to the µC as a single 8-bit register; the modem ensuring that sequential µC reads or writes to the
buffer are routed to the correct locations within the buffer.
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.
The buffer should only be written to while in Tx mode and read from while in Rx mode (except when loading
Frame Sync detection bytes while in Rx mode).
4.4.2 Command Register
Writing to this register tells the modem to perform a specific action or actions, depending on the setting of the
TASK, AQLEV and AQBC bits.
Command Register
7 6 5 4 3 2 1 0
AQBC AQLEV
Reserved
set to '0 0 0'
TASK
When there is no action to perform and not 'powersaved', the modem will be in an 'idle' state. If the modem is
in transmit mode the input to the Tx filter will be connected to V . In receive mode the modem will
BIAS
continue to measure the received data quality and extract bits from the received signal, supplying them to the
de-interleave buffer, otherwise the received data is ignored.
4.4.2.1 Command Register B7: AQBC - Acquire Bit Clock
This bit has no effect in transmit mode.
In receive mode, when a byte with AQBC bit set to '1' is written to the Command Register, and TASK is not
set to RESET, it initiates an automatic sequence designed to achieve bit timing Synchronization with the
received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing
extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing Synchronization is
achieved, until the 'normal' value set by the PLLBW bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition sequence
will be re-started every time that a byte written to the Command Register has the AQBC bit set to '1'.
The AQBC bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH (Search for
Frame Head) task, however it may also be used independently to re-establish clock Synchronization quickly
after a long fade. Alternatively, an SFS or SFH task may be written to the Command Register with the AQBC
bit '0' if it is known that clock Synchronization does not need to be re-established. More details of the bit clock
acquisition sequence are given in section 5.3.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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