Digitally Controlled Analog I/O Processor
12
MX839 PRELIMINARY INFORMATION
4.7.4 DAC CONTROL Register (Hex address $D3)
This register controls the resolution and the number of enabled DAC outputs:
These bits define the input resolutions for each of the four DACs. When 'NBIT DACn' is '0' the
resolution of DACn is 8-Bits. When 'NBIT DACn is '1' the resolution of DACn is 10-Bits.
NBIT DAC1 (Bit 7)
NBIT DAC2 (Bit 6)
NBIT DAC3 (Bit 5)
Reserved for future use. This bit should be set to '0'.
(Bit 4)
These bits allow any one or more of the three DACs to be powered up. When '0' the DACn is
powered down and the output is high impedance. When '1' the DAC is powered on and the
output voltage is defined by the DAC Data Registers.
DAC1 ENABLE (Bit 3)
DAC2 ENABLE (Bit 2)
DAC3 ENABLE (Bit 1)
Reserved for future use. This bit should be set to '0'.
(Bit 0)
4.7.5 DAC1 DATA Register (Hex Address $D4)
4.7.6 DAC2 DATA Register (Hex Address $D5)
4.7.7 DAC3 DATA Register (Hex Address $D6)
The data in these three registers sets the analog voltage at the output of DAC1, DAC2 and DAC3. This data will consist
of one or two bytes depending on the defined input resolution that is set by bits 7, 6 and 5 of the DAC Control Register.
When operating with 10-bit resolution Bit 7 to Bit 2 of the DACn DATA Register second data byte must be set to "0".
4.7.8 A/D CONTROL Register (Hex Address $D7)
This register sets which channels are active and enables conversion mode or read mode.
Reserved for future use. This bit should be set to '0'.
Reserved for future use. This bit should be set to ‘1’.
(Bit 7)
(Bit 6)
When this bit is set to ‘1’ all active channels are continuously sampled and the latest converted
data stored for each channel. When this bit is set to ‘0’ all conversions are stopped so that they
may be read.
READ
(Bit 5)
These bits allow any one or more of the four A/D input channels to be enabled. When '0' the
A/DINn input voltage is not converted. When '1' the A/DINn input is defined as active and the
input voltage is converted. A/D1 must be active for any other channel to be active.
A/D1 ACTIVE (Bit 4)
A/D2 ACTIVE (Bit 3)
A/D3 ACTIVE (Bit 2)
A/D4 ACTIVE (Bit 1)
Reserved for future use. This bit should be set to ‘0’.
(Bit 0)
Table 8: A/D CONTROL Register (Hex Address $D7)
4.7.9 MAG COMP ONE LEVELS (Hex Address $D8)
4.7.10 MAG COMP TWO LEVELS (Hex Address $D9)
4.7.11 MAG COMP THREE LEVELS (Hex Address $DA)
4.7.12 MAG COMP FOUR LEVELS (Hex Address $DB)
Each address controls the relevant numbered A/D magnitude comparator.
The first byte, transmitted with the most significant bit first, sets the magnitude comparator upper reference level and the
second byte sets the magnitude comparator lower reference level.
When a reference level's value is set to '0' its IRQ is disabled.
In general, if a reference level’s value is R (unsigned decimal value of data byte)
R
[ ]
Volts
V
= AV
×
REF
DD
256
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