DVSR CODEC
12
MX802
4.2 Write to Control Register
4.2.1 General Reset
Upon power-up the bits in the MX802 registers will be random (either 0 or 1). A General Reset Command
(01 ) will be required to reset all devices on the C-BUS. It has the following effect on the MX802:
H
Control Register
Set to 00
Set to 00
H
Status Register
H
Clear Store and Play Command Buffers
4.2.2 Direct Access
External circuitry is allowed direct access to the Delta Codec data and sampling clocks, disabling the DRAM
timing circuitry. This permits the Delta Codec section of the MX802 to be used as a Delta Modulation voice
encoder and decoder.
Input audio is encoded and made available at the Encoder Out (ENO) pin. Speech data input to the Decoder
In (DEI) pin is decoded to give voice-band audio at the Audio Output.
Analog output switching remains under the control of the Control Register, but the decoder sampling clock
rate (8kbps to 64kbps) must be provided from an external source to the Decoder Clock (DCK) pin. To ensure
correct filter setting, Decoder Control bits (byte 0, bits 5, 4, 3) should be set to binary 1,1,1, where the
required rate approximates to a multiple of 25kbps.
Both the encoder internal sampling clock rate and input switching (Table 7) remain under the control of the
Control Register. The encoder internal sampling clock rate is available to external circuitry at the Encoder
Clock Out (ECK) pin.
4.2.3 Play Counter
The Play Counter direction may be set to run backward as well as forward. This can be used in a scrambling
system by replaying speech data in reverse order.
4.2.4 DRAM Control
A logic “1” will disable the DRAM Control Timing circuits and associated counters. The C-BUS Interface,
Clock Generator, Delta Codec and filters remain active. This bit should be set to logic “1” when the MX802 is
used in the Direct Access Mode.
Minimum DVSR Codec power consumption is achieved by setting both DRAM Control and Powersave bits to
logic “1.”
4.2.5 Codec Powersave
A logic “1” puts the Delta Codec and filters into Powersave Mode with V
maintained. The Clock
BIAS
Generator, C-BUS Interface, and DRAM Control and Timing remain active.
4.2.6 Command Interrupt Enable
A logic “1” set at the relevant bit will enable Interrupt Requests to the microcontroller when that command
operation is complete.
4.2.7 Store and Play Speech Synchronization
This is intended primarily for Time Domain Scrambling.
4.2.8 Decoder and Encoder Control
This individually sets decoder and encoder sampling clock rates, as well as the source of the audio output.
ꢀ1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480033.008
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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