DVSR CODEC
10
MX802
4.1.3.3 Speech Playback
Speech playback is controlled by similar commands using the Speech Play counters and Play Command
Buffer:
4.1.3.3.1 64 PLAY “N” PAGES – START PAGE “X” (immediate)
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65 PLAY “N” PAGES – START PAGE “X” (buffered)
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As soon as the Play Command had completed, the “Play Command Complete” bit in the Status Register is
set, and an Interrupt Request is generated (if enabled).
If no “next” command is waiting in the Play Command Buffer when a speech play command finishes, a
continuous idle code (0101…0101) will be fed to the delta decoder.
Speech data is stored or recovered at the selected Encode or Decode sample rate (Table 5). Store or Play
Command Complete bits in the Status Register are cleared by the next Store or Play Command received from
the microcontroller, or by a General Reset (01 ).
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4.1.3.4 Store/Play Speech Synchronization (Table 6)
This capability is provided primarily for Time Domain Scrambling applications.
Speech Synchronization bits in the Control Register will produce the effects described below:
4.1.3.4.1 No Speech Sync Set:
Store and Play operations may take place completely independently.
4.1.3.4.2 Store after Play:
The next buffered store command will start on completion of a play command, while the next play command
sequence (if any) continues normally.
4.1.3.4.3 Play after Store:
The next buffered play command will start on completion of a store command, while the next store command
sequence (if any) continues normally.
These actions will continue while Speech Sync bits are set.
4.1.4 Data Handling
For the purpose of storing data sent via C-BUS from the microcontroller, the memory (DRAM) is divided into
“data pages” of 64 bits (8 bytes).
A 256kbit DRAM contains
4096 data pages.
A 1Mbit DRAM contains 16384 data pages.
4Mbit DRAM contains 65536 data pages.
In accordance with C-BUS timing specifications, data is handled 8 bits (1 byte) at a time, although any
number of 8-bit blocks of data may be written to or read from the DRAM by a single command.
Data transfer is terminated by the Chip Select line going to a logic “1.”
4.1.4.1 C-BUS Data Transfer Limitations
For those commands which transfer data over the C-BUS between DRAM and the microcontroller (Write and
Read data), the C-BUS serial clock rate is limited to a maximum of:
125kHz if the VSR Codec is executing store and play commands.
250kHz if no speech Store or Play commands are active.
This limitation is due to the rate at which data goes into and out of the DRAM. All other commands and
replies (Control, Status, Reset) may use a maximum clock rate of 500kHz. See Figure 4.
4.1.4.2 Read Data
4.1.4.2.1 67 READ DATA -- START PAGE “P”
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This command sets the Data Read Counter to “P,” page, and then reads data bytes from successive DRAM
locations, sending them to the microcontroller as Reply Data bytes. The Data Read Counter is incremented
by 1 for each bit read.
4.1.4.2.2 69 READ DATA CONTINUE
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This command reads data bytes from successive DRAM locations determined by the Data Read Counter,
incrementing the counter by 1 for each bit read.
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