DVSR CODEC
15
MX802
4.3.1 Time Compression of Speech
The 25kbps and 50kbps sampling rate options are provided for time compression and subsequent expansion
of speech signals.
For example, 1.0 seconds of speech stored at 50kbps may be transmitted in 0.8 seconds if played out at
64kbps, and finally restored to its original speed at the receiver by storing at 64kbps and playing out at
50kbps. A similar result (with a degraded SINAD) may be achieved by using 25kbps and 32kbps sampling
rates.
However, the speech frequencies are raised by time compression, and since the signal transmitted to air must
be band limited to 3400 Hz, the effective end-to-end bandwidth is 0.8 x 3400 Hz, which is approximately
2700 Hz.
4.4 Read Status Register
4.4.1 Interrupts
If enabled by the Control Register, an Interrupt Request (IRQ) is produced by the MX802 to report the
following actions:
Power Reading Ready
Store Command Complete
Play Command Complete
When an Interrupt is produced, the Status Register must be read to determine the source of the interrupt. This
action will clear the IRQ output.
The Store Command Complete bit (and an interrupt) is set on completion of a Store Command. This bit is
cleared by loading the next Store Command, or by a General Reset Command (01 ).
H
The Play Command Complete bit (and an interrupt) is set on completion of a Play Command. This bit is
cleared by loading the next Play Command, or by a General Reset Command (01 ).
H
The Power Reading Ready bit (and an interrupt) is set for every 1024 voice-data bits (1 page) from the
Encoder. This bit is cleared after reading the Status Register, or by a General Reset Command (01 ).
H
4.4.2 Power Register
The power assessment element shown in Figure 1 assesses the input signal power for each encoded “page”
(every 1024 encoder output bits) by counting the number of “compand bits” (000 or 111 sequences in the
output bit stream) produced during that page (see Table 8) with typical encoder input power levels (dB).
At the end of each “page” the power reading ready bit of the status register is set, and an interrupt request is
generated (if enabled). The resulting count is converted to a 5-bit quasi-logarithmic form. The Power Register
reading is interpreted as follows:
00000 represents 0 compand bits
00001 represents 1 compand bit
11111 represents 512 compand bits, the maximum.
This power reading is placed in the status register to be read by the microcontroller. Figure 4 shows this
output, indicating the input power level.
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