FRS Signalling Processor
CMX882
AC Parameters (cont.)
Notes
Min.
Typ.
Max.
Unit
Auxiliary ADC (Signal Monitor)
8 Bit ADC Mode
Resolution
8
Bits
VDD
µs
Input Range
10%
90%
Conversion time
Input impedance
Resistance
41
20.8
10
5
MΩ
Capacitance
pF
Zero error
(input offset to give ADC output = 0)
+20
2
mV
LSB
LSB
LSB
LSB
kΩ
−20
Integral Non-linearity
42
43
4
Differential Non-linearity
Source output impedance
1
42
3
43
44
24
Level Threshold Detect Mode
Threshold Resolution
8
Bits
V
Upper threshold range (VTH)
Lower threshold range (VTL)
Signal Monitor change to IRQ
Signal Monitor change to Receiver-Turn-On
45
45
46
47
VTL
VDD(A)
VTH
120
VSS(A)
V
µs
µs
60
Audio Compandor
Attack time
4.0
13
ms
ms
Decay time
0dB point
48
100
2:1
mVrms
Compression / Expansion ratio
41
42
43
44
With clock frequency of 18.432MHz.
VDD(A) ≥ 3.0V
Notes:
VDD(A) < 3.0V
Denotes output impedance of the driver of the Signal Monitor input, to ensure < 1
bit additional error under nominal conditions.
45
46
Upper threshold > Lower threshold
Time from Signal Monitor input rising above Upper Threshold or falling below
Lower Threshold, to IRQN being asserted.
47
48
Time from Signal Monitor input rising above Upper Threshold to receiver path
powering up, settling and starting automatic signal type identification.
VDD(A) = 3.0V
2004 CML Microsystems Plc
63
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
