FRS Signalling Processor
CMX882
Operating Characteristics
For the following conditions unless otherwise specified:
External components as recommended in Figure 2.
Maximum load on digital outputs = 30pF.
Xtal Frequency = 18.432MHz ±0.01% (100ppm).
VDD = 2.7V to 3.6V; Tamb = −40°C to +85°C.
Reference Signal Level = 308mV rms at 1kHz with VDD = 3V.
Signal to Noise Ratio (SNR) in bit rate bandwidth.
Input stage gain = 0dB.
Output stage attenuation = 0dB.
DC Parameters
Notes
Min.
Typ.
Max.
Unit
Supply Current
IDD(D) (VDD = 3.0V)
21
21
21
21
4.5
1.0
2.0
2.0
8.0
2.0
10
mA
mA
µA
IDD(A) (VDD = 3.0V)
IDD(D) (All Power-saved) (VDD = 3.0V)
IDD(A) (All Power-saved) (VDD = 3.0V)
10
µA
C-BUS Interface
Input Logic ‘1’
70%
VDD
VDD
µA
Input Logic ‘0’
30%
1.0
Input Leakage Current (Logic ‘1’ or ‘0’)
Input Capacitance
−1.0
-
7.5
pF
Output Logic ‘1’
Output Logic ‘0’
(IOH = 120µA)
(IOL = 360µA)
90%
VDD
VDD
µA
10%
10
“Off” State Leakage Current
IRQN
(Vout = VDD(D))
1.0
1.0
µA
−1.0
−1.0
REPLY_DATA (output HiZ)
µA
CLOCK_OUT
Output Logic ‘1’
(IOH = 120µA)
90%
80%
VDD
VDD
VDD
VDD
(IOH = 1mA)
Output Logic ‘0’
(IOL = 360µA)
(IOL = -1.5mA)
10%
15%
22
23
CLOCK/XTAL
Input Logic ‘1’
70%
−40
-2%
VDD
VDD
µA
Input Logic ‘0’
30%
40
Input current (Vin = VDD
)
Input current (Vin = VSS
)
µA
VBIAS
+2%
VDD
kΩ
Output voltage offset wrt VDD/2 (IOL < 1µA)
Output impedance
22
21
22
23
Not including any current drawn from the device pins by external circuitry.
Notes:
Characteristics when driving the CLOCK/XTAL pin with an external clock source.
Applies when utilising VBIAS to provide a reference voltage to other parts of the
system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must
always be decoupled with a capacitor as shown in Figure 2.
2004 CML Microsystems Plc
60
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
