FRS Signalling Processor
CMX882
AC Parameters
Notes
Min.
Typ.
Max.
Unit
CLOCK/XTAL Input
'High' pulse width
'Low' pulse width
31
31
21
21
ns
ns
Input impedance (at 18.432MHz)
Powered-up
Resistance
Capacitance
Resistance
Capacitance
150
20
kΩ
pF
Powered-down
300
kΩ
20
pF
Clock frequency
18.432
MHz
Clock stability/accuracy
±100
ppm
ms
Clock start up (from power-save)
400
CLOCK_OUT Output
CLOCK/XTAL input to CLOCK_OUT timing:
(in high to out high)
32
32
33
33
15
15
ns
ns
ns
ns
(in low to out low)
'High' pulse width
22
22
27.13
27.13
33
33
'Low' pulse width
V
BIAS
Start up time (from power-save)
30
1
ms
Microphone, Input_2 and Disc Inputs
(MIC, INPUT_2, DISC)
Input impedance
34
35
MΩ
%VDD
kΩ
Input signal range
10
80
90
Load resistance (pin 12, 14 and 16)
Amplifier open loop voltage gain
(I/P = 1mV rms at 100Hz)
60
dB
Unity gain bandwidth
Programmable Input Gain Stage
Gain (at 0dB)
1.0
MHz
36
0
0.5
1.0
dB
dB
−0.5
−1.0
Cumulative Gain Error
(wrt attenuation at 0dB)
31
32
33
34
35
36
Timing for an external input to the CLOCK/XTAL pin.
CLOCK/XTAL input driven by external source.
18.432MHz XTAL fitted.
Notes:
With no external components connected
After multiplying by gain of input circuit, with external components connected.
Gain applied to signal at output of buffer amplifier, pin 12, 14 or 16
2004 CML Microsystems Plc
61
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
