FRS Signalling Processor
CMX882
8
1.6.15
Bit:
$CE INTERRUPT MASK: 16-bit write-only
15
14
13
12
11
10
9
IRQ
Rx In-band
Rx CTCSS
Rx DCS
Aux ADC High Aux ADC Low
0
XTCSS MASK
MASK
detect MASK
detect MASK detect MASK
MASK
MASK
7
6
5
0
4
3
2
0
1
0
0
Bit:
FFSK end
MASK
Data transfer
MASK
Rx 2400b/s
Rx 1200b/s
Prog Flag
MASK
detect MASK detect MASK
Bit
15
Value Function
1
0
Enable selected interrupts
Disable all interrupts (IRQN pin not activated)
Reserved – Set to 0
14
13
1
Enable interrupt when a change to a In-band tone is detected as indicated
by a '0' to '1' change of bit 13 of the Status register
Disabled
0
1
12
Enable interrupt when a valid XTCSS 4 tone set is detected or has
finished being transmitted as indicated by a '0' to '1' change on bit 12 of
the Status register
0
1
Disabled
11
10
Enable interrupt when a change to a programmed CTCSS tone is
detected as indicated by a '0' to '1' change of bit 11 of the Status register
0
1
Disabled
Enable interrupt on a change in the detect status of the DCS decoder as
indicated by a '0' to '1' change of bit 10 of the Status register
0
1
0
1
0
1
0
Disabled
9, 8
7
Enable interrupt when the corresponding Aux ADC status bit changes
Disabled
Enable interrupt when FFSK data transmission has ended
Disabled
6
Enable interrupt when an FFSK data transfer is required
Disabled
Reserved - Set to 0
5
4
1
0
1
0
Enable interrupt when valid 2400b/s data is detected
Disabled
3
Enable interrupt when valid 1200b/s data is detected
Disabled
Reserved - Set to 0
2, 1
0
1
0
Enable interrupt when Prog Flag bit of the Status register changes from '0'
to '1' (see Programming register $C8)
Disabled
2004 CML Microsystems Plc
46
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
