“Write to Control Register”
–
Setting
Byte 1
(MSB)
Bit 7
6
1
Function
Address/Command 60
H
, followed by 2 bytes of Command Data
General Reset
Upon Power-Up the “bits” in the FX802 registers will be
random (either “0” or “1”). A General Reset command (01
H
)
will be required to “reset” all microcircuits on the “C-BUS,”
and has the following effect upon the FX802:
Control Register
Set as 00
H
Status Register
Set as 00
H
Clear Store and Play Command Buffers
First Byte for Transmission
Not used – Set to “0”
Direct Access
– Encoder Data Out to A0/ENO
– Encoder Clock to A3/ECK
– Decoder Input from A1/DEI
–
Decoder Clock from A2/DCK
Normal DVSR Operation
Play Counter
Decrement
Increment
DRAM Control
Disable DRAM
Enable DRAM
Codec Powersave
Powersave Delta Codec
Enable Delta Codec
Store Command Interrupt
Enable Interrupt
Disable
Play Command Interrupt
Enable Interrupt
Disable
Power Reading Interrupt
Enable Interrupt
Disable
Direct Access
Allows external circuitry “Direct Access” to the Delta Codec
data and sampling clocks, disabling the DRAM timing
circuitry. This permits the Delta Codec section of the FX802
to be used as a “stand-alone” delta modulation voice
encoder and decoder.
Input Audio is encoded and made available at the
Encoder Out (ENO) pin. Speech data input to the Decoder
In (DEI) pin is decoded to give voice-band audio at the
Audio Output.
The following points, with respect to Control Register
settings, should be considered. Analogue output switching
remains under the control of the Control Register, but the
Decoder sampling clock rate (8kbit/s to 64kbit/s) must be
provided from an external source to the Decoder Clock
(DCK) pin. To ensure correct filter setting, Decoder Control
bits (Byte 0, Bits 5, 4, 3) should be set to (binary) 1, 1, 1,
where the required rate approximates to a multiple of
16kb/s, or (binary) 1, 1, 0, where the required rate
approximates to a multiple of 25kb/s.
Both the Encoder internal sampling clock rate and
input switching (Table 5) remain under the control of the
Control Register. The sampling clock rate is available to
external circuitry at the Encoder Clock Out (ECK) pin.
0
5
1
0
4
1
0
3
1
0
2
1
0
1
1
0
0
1
0
Byte 0
(MSB)
7
0
0
1
1
5
0
0
0
0
1
1
1
1
2
0
0
0
0
1
1
1
1
4
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
6
0
1
0
1
3
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
Play Counter
The Play Counter direction may be set to run backwards as
well as forwards. This can be used in a scrambling system
by replaying speech data in reverse order.
Last Byte for Transmission
Store/Play Speech Sync
No Sync
No Sync
Sync – Play after Store
Sync – Store after Play
Decoder Control
Idle (32kbit/s); Aud O/P via L.P.F.
Idle (32kbit/s); Aud By-Pass
Idle (32kbit/s); Aud O/P at High Z
On – Sampling Rate 16kbit/s
On –
"
25kbit/s
On –
"
32kbit/s
On –
"
50kbit/s
On –
"
64kbit/s
Encoder Control
– F/Idle (32kbit/s)
I/P at V
BIAS
I/P at High Z – F/Idle (32kbit/s)
I/P at High Z – F/Idle (32kbit/s)
On – Sampling Rate 16kbit/s
On –
"
25kbit/s
On –
"
32kbit/s
On –
"
50kbit/s
On –
"
64kbit/s
DRAM Control
A logic “1” will disable the DRAM Control timing
circuits and associated counters. The “C-BUS” Interface,
Clock Generator, Delta Codec and filters remain active.
This bit should be set to logic “1” when the FX802 is used in
the Direct Access mode.
Minimum DVSR Codec power consumption is
achieved by setting both DRAM Control and Powersave
bits to a logic “1.”
Codec Powersave
A logic “1” puts the Delta Codec and filters into a
Powersave mode, with V
BIAS
maintained.
The Clock Generator, “C-BUS” Interface and DRAM
Control and Timing remain active.
Command Interrupt Enable
A logic “1” set at the relevant bit will enable Interrupt
Requests to the
µController
when that command operation
is complete.
Store and Play Speech Synchronization
Intended, primarily, for Time Domain Scrambling.
Decoder and Encoder Control
Sets individually, decoder and encoder sampling clock
rates and the source of the Audio Output.
Table 4 Control Register
8
CMLMICRO [ CML MICROCIRCUITS ]
