Controlling Protocol ......
Data Operations
Data Storage and Recovery
For the purpose of storing data sent via “C-BUS” from the
µC,
the memory (DRAM) is divided into ‘data-pages’ of
64-bits (8-bytes).
A single 256kbit DRAM contains
4096 data-pages.
A single 1Mbit DRAM contains
16384 data-pages.
4Mbit DRAM contains
65536 data-pages.
In accordance with “C-BUS” timing specifications, data
is handled 8-bits (1-byte) at a time although any number
of 8-bit blocks of data may be written-to or read-from the
DRAM by a single command.
The data transfer action is terminated by the Chip
Select line being taken to a logic “1.
“C-BUS” Data Transfer Limitations
For those commands which transfer data over the
“C-BUS” between DRAM and the
µController
(Write and
Read Data) the “C-BUS” Serial Clock rate is limited to a
maximum of:
125kHz if the VSR Codec is executing Store and
Play commands.
250kHz if no speech Store or Play commands are
active.
All other commands and replies (Control, Status,
General Reset) may use a maximum clock rate of
500kHz. See Figure 5.
Read and Write Data actions are explained below
Read Data
67
H
READ DATA – START PAGE “P”
Write Data
66
H
WRITE DATA – START PAGE “P”
Sets the Data Read Counter to “P” page and then
reads data bytes from successive DRAM locations,
sending them to the
µC
as Reply Data bytes
incrementing the Data Read Counter by 1 for each bit
read.
69
H
READ DATA – CONTINUE
Sets the Data Write Counter to “P” page and then
writes data bytes to successive DRAM locations,
incrementing the Data Write Counter by 1 for each bit
received via the “C-BUS.”
The Start Page “P,” is indicated by loading a 2-byte
word after the relevant Address/Command byte. This
16-bit word allows data-page addresses from 0 to 65535
(4Mbits DRAM).
68
H
WRITE DATA – CONTINUE
Reads data bytes from successive DRAM locations
determined by the Data Read Counter incrementing the
counter by 1 for each bit read.
Writes data bytes to successive DRAM locations
determined by the Data Write Counter, incrementing the
counter by 1 for each bit received over the “C-BUS.”
Encoder and Decoder Sampling Clocks
Encoder and decoder sampling clock rates are programmable via the Control Register. Table 3 shows the range of
sampling rates available for differing Xtal/clock input frequencies, and the counter ratios used to produce them.
If different “Store and Play” sampling rates are used in a single operation, only combinations of 25kb/s with 32kb/s or
50kb/s with 64kb/s will give correct output levels in accordance with current specifications. Consideration should be given
to the effect of differing Xtal/clock frequencies upon the audio frequency performance of the device.
Xtal/clock Frequency (MHz)
Control Register
Byte 0, Bits
5
4
3 Dec.
2
1
0 Enc.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
4.0
Internal Counter
Division
Ratio
256
160
128
80
64
15.625
25.0
31.25
50.0
62.50
4.032
Sampling Rate
(kbits/s)
15.75
25.20
31.50
50.4
63.0
16.0
25.60
32.0
51.20
64.0
4.096
Table 3 Sampling Clock Rates Available
With respect to using a single Xtal/clock frequency for all DBS 800 devices in use it should be noted that:
(a) a 4.032MHz Xtal/clock input will produce an accurate 1200 baud rate for the FX809 FFSK Modem
(b) a 4.096MHz Xtal/clock input will generate exactly 16kb/s and 32kb/s Codec sampling clock rates.
7
CMLMICRO [ CML MICROCIRCUITS ]
