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FX802 参数 Datasheet PDF下载

FX802图片预览
型号: FX802
PDF下载: 下载PDF文件 查看货源
内容描述: DVSR CODEC [DVSR CODEC]
分类和应用: 晶体晶体管开关光电二极管
文件页数/大小: 14 页 / 129 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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External Components
V
DD
C
5
4 x 1Mbit
DRAM
A0 – A9
WE
CAS
RAS
D
Q
V
SS
RAS2
R
1
1 §
2
3
4 §
5
6
7
8
9
10
11
12
13
14
V
DD
28
27
26
§ 25
§ 24
23
22
CAS
A9
RAS3
RAS4
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
A1/DEI
A0/ENO
RAS1
WE
XTAL
See INSET
XTAL/CLOCK
IRQ
SERIAL CLOCK
A0 – A9
WE
CAS
RAS
D
Q
C-BUS
INTERFACE
COMMAND DATA
CS
REPLY DATA
V
BIAS
AUDIO OUT
AUDIO IN
C
4
C
6
V
SS
FX802J
21
20
19
18
17
16
15
A0 – A9
WE
CAS
RAS
D
Q
C
1
R
3
V
SS
A0 – A9
WE
CAS
RAS
D
Q
INSET
XTAL
Component
Value
22.0kΩ
1.0MΩ
1.0kΩ
1.0µF
33.0pF
33.0pF
C
4
C
5
C
6
X
1
=
1.0µF
1.0µF
1.0nF
4.00MHz
4.032MHz
4.096MHz
X
1
R
2
FX802J
XTAL/CLOCK
C
3
C
2
V
SS
5
R
1
R
2
R
3
C
1
C
2
C
3
=
or
or
Tolerance: R =
±10%
C =
±20%
Fig.2 Recommended Component and DRAM Connections
Notes
1. Xtal circuitry shown INSET is in accordance with CML
Application Note D/XT/2 December 1991.
2. External Xtal circuitry is not applicable to the 24-pin/lead
versions of this device, only a clock pulse input can be
used.
3. Functions whose pins are marked § above are not
available on the 24-pin/lead versions of this device. Pin
numbers illustrated are for 28-pin versions.
4. Table 3 details the actual encoder/decoder sample rates
available using the Xtal frequencies recommended above.
5. R
1
is used as the DBS 800 system common-pullup for the
“C-BUS” Interrupt Request (IRQ) line, the optimum value
will depend upon the circuitry connected to the IRQ line.
Up to 8 peripherals may be connected to this line.
6. Recommended DRAM Parameters:
256kbit x 1 or 1Mbit x 1 Dynamic Random Access Memory
with ‘CAS before RAS’ refresh mode, maximum Row
Address Access time = 200nsec.
Example DRAM types:
256kbit (262,144bits)
Texas Instruments
Hitachi
1Mbit (1,048,576bits)
Texas Instruments
Hitachi
TMS4256–20
HM51256–15
TMX4C1024–15
HM511000–15
7. Figure 2 (above) shows connections to 4 x 1Mbit sections
of DRAM. If desired, to simplify PCB layout, the DRAM
inputs A0 to A8 may be connected in any order to the
FX802 DVSR Codec output pins A0 to A8. Connections to
256kbit DRAM are similar, but A9 unconnected.
8. When using the FX802 “stand-alone (Direct Access),” no
DRAM should be connected.
4