Specification ......
Characteristics
Serial/Parallel Inputs
Parallel Set-Up Time (t
SP
)
Load/Latch Pulse Width (t
L
)
Serial Clock Pulse Width (t
C
)
Serial Set-Up Time (t
SS
)
Serial Enable Time (t
1
)
Serial Load/Latch Set-Up Time (t
2
)
Serial Clock Frequency
Notes
1.
2.
3.
4.
5.
6.
7.
8.
Refers to Rx/Tx, PTL, Decode Comparator Input, D
0
, D
1
, D
2
, D
3
, D
4
, D
5
inputs.
All logic outputs.
Composite Signal test condition.
Any programme tone and RL = 600Ω. CL = 15pF. Includes response to a phase-reversal instruction.
1kHz reference = 0dB.
f
O
> 100Hz, (for 100Hz >f
O
>67Hz: t = (100/f
O
Hz) x 250ms).
Measured in a 30kHz bandwidth.
For an input level of 180mVrms at 1.0kHz, in a 30kHz measurement bandwidth.
See Note
Min.
400
400
400
400
400
400
-
Typ.
-
-
-
-
-
-
1.0
Max.
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
MHz
(a) Parallel Mode Timing
D
0
to D
5
, Rx/Tx and PTL
t
L
LOAD/LATCH
t
SP
For wired, non-µP applications,
Load/Latch should be connected to V
DD
.
(b) Serial Mode Timing
D
5
SERIAL
ENABLE
FUNCTION
D
4
Data load sequence: D5, D4, D3, D2, D1, D0, Rx/Tx and PTL/Phase Reverse
t
1
SERIAL
DATA
D
3
DATA D
5
t
W
DATA D
4
t
C
SERIAL
CLOCK
D
2
t
SS
D
1
and D
0
NOT USED
1.0MΩ INTERNAL PULLUP
t
2
t
L
LOAD/LATCH
D
3
Rx/Tx
(Rx) PTL or
(Tx) Phase Reverse
LOAD DATA
LATCH DATA
Fig.4 Serial and Parallel Timing Diagrams
7
DATA LATCHED
CMLMICRO [ CML MICROCIRCUITS ]
