Pin Number
FX365C
1
DW, J, LG and LS package styles
Function
V
DD
:
Positive supply rail. A single stable supply is required; levels and voltages within the FX365C are
dependent upon this supply.
This pin should be decoupled to V
SS
by a capacitor located close to the pin.
2
Xtal/CIock:
Input to the on-chip inverter; used with a 1.0MHz Xtal or external clock source.
3
Xtal:
Output of the on-chip clock oscillator inverter.
4
Load/Latch:
Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D
0
- D
5
. This pin is internally
pulled to V
DD
. A logic ‘1’ applied to this input places the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input places the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4a).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4b).
5
D
5
/Serial Enable 1:
Data input D
5
(Parallel Mode); Serial Enable 1 (Serial Mode).
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D
4
/Serial Enable 2, will put the device
into 'Serial Mode' (see Figure 4b). This pin is internally pulled to V
DD
.
6
D
4
/Serial Enable 2:
Data input D
4
(Parallel Mode); Serial Enable 2 (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D
5
/Serial Enable 1, will place the
device into ‘Serial Mode’ (see Figure 4b). This pin internally pulled to V
DD
.
7
D
3
/Serial Data:
Data input D
3
(Parallel Mode); Serial Data Input (Serial Mode).
In Serial Mode this pin becomes the serial data input for D
5
- D
0
, Rx/Tx, PTL (see Figure 4b). D
5
is
clocked-in first and PTL last. This pin internally pulled to V
DD
.
8
D
2
/Serial Clock:
Data input D
2
(Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge
(see Figure 4b). This pin is internally pulled to V
DD
.
9
D
1
:
Data input D
1
(Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to V
DD
.
10
D
0
:
Data input D
0
(Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to V
DD
.
11
V
SS
:
Negative supply (GND).
12
Decode Comparator Ref.
(I/P): Internally biased to V
DD
/3 or 2V
DD
/3 via 1.0MΩ resistors depending
on the logical state of the Tone Decode Output pin, this input provides the decode comparator
reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal
conditions. Tone Decode Output = logic ‘1’ will place this input to 2V
DD
/3 bias, a logic ‘0’ will bias this
input to V
DD
/3.
2
CMLMICRO [ CML MICROCIRCUITS ]
