Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to
D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/
Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,
6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for
output settings (D0-D3). This format is illustrated below in Figure 4.
Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection
and output settings, respectively.
D13
D12
D12
D10
D9
D8
D7
D6
D5
INPUT
SELECT
D4
D3
D2
D1
D0
GAIN/ATTENUATION
LEVEL
CHANNEL
ADDRESS
OUTPUT
SETTINGS
Fig.4 Level-Controlling Data Word Format
D13 D12 D11 D10
Gain
Set (dB)
0
0
0
0
0
0
MUTE
0
0
0
0
0
1
-48
0
0
0
0
1
0
-46
0
0
0
0
1
1
-44
0
0
0
1
0
0
-42
0
0
0
1
0
1
-40
0
0
0
1
1
0
-38
0
0
0
1
1
1
-36
0
0
1
0
0
0
-34
0
0
1
0
0
1
-32
0
0
1
0
1
0
-30
0
0
1
0
1
1
-28
0
0
1
1
0
0
-26
0
0
1
1
0
1
-24
0
0
1
1
1
0
-22
0
0
1
1
1
1
-20
0
1
0
0
0
0
-18
0
1
0
0
0
1
-16
0
1
0
0
1
0
-14
0
1
0
0
1
1
-12
0
1
0
1
0
0
-10
0
1
0
1
0
1
-8
0
1
0
1
1
0
-6
0
1
0
1
1
1
-4
0
1
1
0
0
0
-2
0
1
1
0
0
1
0
Table 1 - Amplification/Attenuation Level
D9
D8
D13 D12 D11 D10
D9
D8
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gain
Set (dB)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
48
48
D7
0
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 2 Stage and Input Selection
Stage
Selected
1
2
D6
D5
D4
0
1
0
1
0
1
0
1
Inputs
Selected
none
1
2
1 and 2
3
1 and 3
2 and 3
1, 2 and 3
Output
D1
1B
0
0
high Z
0
0
1
enabled
0
1
0
V
SS
1
1
1
V
BIAS
1
Table 3 Stage Output Selection
D3 D2
D0
0
1
0
1
Outputs
1A & 2
high Z
enabled
V
SS
V
BIAS
4
CMLMICRO [ CML MICROCIRCUITS ]
