Application Information
External Components
V
DD
SERIAL CLOCK
SERIAL DATA
LOAD/LATCH
IN 1A
IN 1B
IN 2A
IN 2B
C
1
C
2
C
3
C
4
V
SS
8
1
2
3
4
16
15
14
13
V
DD
IN 3
OUT 3
C
7
V
SS
OUT 1A
OUT 1B
OUT 2
C
5
V
BIAS
IN 1C
FX029
5
6
7
DW/J
12
11
10
9
V
SS
Fig.2 Recommended External Components
Component Recommendations
Component
Value
C
1
0.1µF
C
2
0.1µF
C
3
0.1µF
C
4
0.1µF
C
5
0.1µF
C
6
Not Used
C
7
1.0µF
Tolerances 20%
Input capacitors C
1
to C
5
are only required for ac
input signals; dc input signals do not require these
components.
The gain of the uncommitted stage (3) is set by
external components employed around the input and
output pins (see Specification page).
Application Recommendations
To avoid noise and instability the following practices
are recommended:
(a) Use a clean, well-regulated power supply.
(b) Keep tracks short.
(c) Inputs and outputs should be shielded wherever
possible.
(d) Analogue tracks should not run parallel to digital
tracks.
(e) A “Ground Plane” connected to V
SS
will assist in
eliminating external pick-up on the channel input
and output pins.
(f) Avoid running high level outputs adjacent to low
level inputs.
(g) The serial clock should not be running
consecutively when not in the process of actually
loading data.
Serial Interface Timing
SERIAL
CLOCK
t
PWH
t
PWL
1ST
CLOCK
PULSE
14TH
CLOCK
PULSE
SERIAL
DATA
t
DS
D13
t
DH
D12
D1
D0
LOAD/LATCH
t
LLD
t
LLO
Fig.3 Serial Timing Diagram - see Specification page for timing specifications
3
t
LLW
CMLMICRO [ CML MICROCIRCUITS ]
