Marine VHF Audio and Signalling Processor
CMX885
8.1.22 Status – $C6 read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Aux
Aux Data Data
IRQ NWR res DTMF res
b15 IRQ
res ADC2 ADC1 End RDY
res
res
DSC
res
res
PRG
Changes in the Status register will cause this bit to be set to 1 if the corresponding interrupt
mask bit is enabled. An interrupt request is issued on the IRQN pin when this bit is 1 and the
IRQ MASK bit (b15 of Interrupt Mask register, $CE) is set to 1.
b14 NWR status change
The NOAA Weather Receiver has detected a change in the status of the WAT tone or SAME
data. The NWR data/status register $BB should be read to determine the exact cause.
b13 reserved
b12 DTMF event
A valid DTMF tone has been detected and can be read from the Tone Status register, $CC.
b11 reserved
b10 reserved
b9 AuxADC2 Threshold change
AUX ADC2 signal has just gone above the high threshold or has just gone below the low
threshold. The AuxADC2 data register $AA should be read to determine the exact cause.
b8 AuxADC1 Threshold change
AUX ADC1 signal has just gone above the high threshold or has just gone below the low
threshold The AuxADC1 data register $A9 should be read to determine the exact cause.
b7 Data End
Rx mode: this bit is not used, so its value should be ignored. See section 7.7.1.
Tx mode: this will be set when the last bit of DSC data has been transmitted. After allowing a
short time delay associated with the external components and radio circuitry, the host may
power down the CMX885 and transmitter or set the CMX885 to transmit or receive new
information as appropriate.
b6 Data Ready
Tx mode: indicates that new transmit data is required.
Rx mode: received data is ready to be read.
For continuous transmission or reception of information, a data transfer should be completed
within the time appropriate for that data.
b5 reserved
b4 reserved
b3 DSC
When set to 1, this bit indicates that a valid DSC data sequence has been received.
b2 reserved
b1 reserved
b0 PRG
When set to 1, this bit indicates that the Programming register, $C8 is available for the host to
write to it. Cleared by writing to the Programming register, $C8
Bits 2 to 15 of the Status register are cleared to 0 after the Status register is read.
The data in this register is not valid if bit 5 of the Power Down Control register, $C0 is set to 1.
© 2010 CML Microsystems Plc
45
D/885/3
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