Marine VHF Audio and Signalling Processor
CMX885
7
Detailed Descriptions
Device Ident Code
7.1
Following a Power-on or Reset (see section 8.1.1), the device will report the Device Ident Code in the
Tone Status register ($CC) to indicate that it is operational.
7.2
Xtal Frequency
The CMX885 is designed to work with a Xtal of 3.6864MHz. If this default configuration is not used, then
Program Block 3 (see section 8.2.4) should be loaded with the correct values to ensure that the device
will work to specification with the user specified clock frequency. A table of common values can be found
in Table 2. Note the maximum Xtal frequency is 12.288MHz, although an external clock source of up to
24.576MHz can be used.
The register values in Table 1 are shown in hex (however only the lower 10 bits are relevant), the default
settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable
limits) are in italics. The new P3.2-3 settings take effect following the write to P3.3 (the settings in P3.4-7
are implemented on a change to Rx or Tx mode).
Table 2 Xtal/clock Frequency Settings for Program Block 3
Program Block
External Frequency Source (MHz)
3.6864
$01C
6.144
$018
9.216
$018
12.0
12.8
16.368
16.8
19.2
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
GP Timer
$019
$019
$018
$019
$018
VCO output and
AUX clk divide
$084
$030
$280
$13C
$008
$088
$040
$200
$140
$008
$08C
$060
$200
$140
$008
$10F
$07D
$200
$140
$008
$110
$0C8
$300
$140
$008
$095
$155
$400
$140
$008
$115
$15E
$400
$140
$008
$099
$0C8
$200
$140
$008
Ref clk divide
PLL clk divide
VCO output and
AUX clk divide
Internal ADC /
DAC clk divide
7.3
Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the CMX885 and
the host µC; this interface is compatible with Microwire and SPI. Interrupt signals notify the host µC when
a change in status has occurred and the µC should read the status register across the C-BUS and
respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 7.14.1.
The CMX885 will monitor the state of the C-BUS registers that the host has written to every 250µs (the C-
BUS latency period) hence it is not advisable for the host to make successive writes to the same C-BUS
register within this period.
To minimise activity on the C-BUS interface, optimise response times and ensure reliable data transfers, it
is advised that the IRQ facility be utilised (using the IRQ mask register, $CE). It is permissible for the host
to poll the IRQ pin if the host µC does not support a fully interrupt-driven architecture. This removes the
need to continually poll the C-BUS status register ($C6) for status changes.
The C-BUS block provides for the transfer of data and control or status information between the
CMX885’s internal registers and the host µC over the C-BUS serial interface. Each transaction consists of
a single Address byte sent from the µC which may be followed by one or more Data byte(s) sent from the
µC to be written into one of the CMX885’s Write Only Registers, or one or more data byte(s) read out
from one of the CMX885’s Read Only Registers, as illustrated in Figure 4.
Data sent from the µC on the CDATA line is clocked into the CMX885 on the rising edge of the SCLK
input. RDATA sent from the CMX885 to the µC is valid when SCLK is high. The CSN line must be held
© 2010 CML Microsystems Plc
14
D/885/3
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